CICC ES2-1 - "IC Design after Moore's Law" - Dr. Greg Yeric

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Abstract:
In this session we’ll discuss the outlook for Moore’s Law scaling and the resulting challenges and opportunities for circuit design.
From today’s 7nm processes, with FinFETs and EUV, we’ll examine the increasingly complex scaling paths that may enable several more Moore’s Law nodes. But at the same time, new technologies will likely provide us additional scaling tools in the near term and in the far term. In the near term advanced packaging techniques and novel non-volatile memories are becoming available, and in the far term we may see entirely different compute technologies such as spintronics, cryogenic computing, and photonics. In discussing these “More Moore” and “More than Moore” options, we’ll find that the era beyond 10nm CMOS will be fertile ground for the circuit designer.
Biography: Greg Yeric earned his BSEE, MSEE, and PhD in Microelectronics right here in the great city of Austin, Texas. He began his career at Motorola’s Advanced Products Research and Development Laboratories in the area of process integration, subsequently working at TestChip Technologies, HPL Technologies, and Synopsys, in the areas of test structures and yield analysis. For the last 11 years, he has been at ARM Research, where he is an ARM Fellow focusing on future manufacturing technologies and their interaction with design. Outside of ARM he volunteers on the VLSI Technology Symposium technical program committee and also on the Microsystems Exploratory Council for the Microsystems Technology Office of DARPA.

[@calengr1]

6:44 where we are vs Moore Law; 8:15 50K drops in EUV laser

[@PedramNG]

Oh, this is like a heaven for me 😂👍👍👍

[@calengr1]

5:42 OVERVIEW; 7:40 EUV works for single patterning

[@kdalkafoukis]

amazing talk

[@calengr1]

17:48 Zeiss mirror test chamber

[@alterguy4327]

41:42

[@LivingTheDream77]

Is there an updated version of this presentation for 2021 ?

[@carl8790]

Not really. Probably in the next 4-5 years.

[@ixion2001kx76]

1:10:30 If the resistors aren’t linear, that nonlinearity will contribute to the activation function’s necessary nonlinearity. Depending on what sort of nonlinearity is involved, that may be acceptable and would mean the model is only portable to other hardware with the same underlying technology

[@belaliqbal8858]

That non-linearity extent is available in the model (PVT variation) and you can visualize this by running monte Carlo simulations. While training your algorithm you can model those non-linearities as noise. These trained data worked with this particular technology only. Once you change your technology, the non-linearities involved would get changed and you again have to train your algorithm.

[@calengr1]

29:45 will 2 nm path be worth it?

[@hammerheadcorvette4]

28:35 Ruthenium mine futures you say????? $$$$$