CICC ES2-4 "ESD Challenges in Advanced FinFET & GAA Nanowire CMOS technologies" - Dr. Shih-Hung Chen

Abstract:
Enabling faster and more compact CMOS transistors, technology scaling has been continually driven for several decades. Bulk FinFET has been a mainstream CMOS technology at the 22/16nm nodes in the semiconductor industry because of improved channel electrostatic and leakage control. ESD reliability has been investigated in bulk FinFET and is strongly impacted by newly introduced process options in these advanced technologies. The process options include the self-align multiple patterning lithography, local interconnect (LI) defined contact scheme, and S/D epitaxial growth in different process modules. The process options have impacts on ESD failure level, clamping voltage and turn-on efficiency. Besides of ESD reliability, the I/O transistors concerning about latch-up (LU) prevention are also influenced by the specific process options in these bulk FinFET technologies.
Next to the FinFET technology, a gate-all-around (GAA) technology is a promising candidate for sub-7nm nodes. This new device architecture will also bring impacts on ESD device characteristics. In this tutorial, we will look at the influence of the device architectures and the corresponding process options on ESD device characteristics in the FinFET/GAA technologies. 3D TCAD simulations bring an in-depth physical understanding of the ESD current conduction and failure mechanism in the ESD protection devices.
Biography: Shih-Hung Chen received the M.S. degree from the Institute of Material Science and Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2002, and the Ph.D. degree from the Institute of Electronics, National Chiao Tung University, in 2009.
In 2002, he joined the Department of ESD and Product Engineering, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, as an ESD Design Engineer. Since 2010, he has been with Device Reliability and Electric Characterization (DRE) Group at IMEC, as a senior ESD researcher. He authored or co-authored more than 100 conference and journal publications. He is a peer reviewer for the IEEE Transactions on Electron Devices, IEEE Electron Device Letters, and IEEE Transactions on Device and Materials Reliability. He has also served as a technical program committee (TPC) member in IEEE International Reliability Physics Symposium (IRPS) since 2016, in EOS/ESD Symposium since 2014, and in IEEE International Symposium on Quality Electronic Design (ISQED) since 2013 and has also served as Session Chair of Emerging Devices and Technologies (EDT) in ISQED since 2017.
His current research interests include ESD protections in advanced sub-10nm technologies, in 3D/2.5D IC applications, and in System Technology Co-Optimization (STCO) with the integrations of III-V materials.

[@charlesr.1920]

Great Presentation helpful details around ESD risk, got some fin damage issues we are working on a with 16nm FinFET Device. Very helpful.