This was a dummy board so there was not a special rule to set (as far as I recall)... I don't know if there is a setting in the Preferences that would limit this overlap, but I regularly place the cage and connector in the same region without problems.
Similar usage in that they have Rx and Tx lanes but does not need the cage like you say. Fiber can plug directly into the coupler end of these transceivers.
Thanks very much for this timely video. I am looking forward to the video where you update a legacy design to use SFPs. Any idea when this is going to be published? Also, would you be willing to share the origin of the layout you presented in your video so I can take a closer look (time 9:23 in video)?
Great timing! I'm working on a 25GBase card and ... First rev doesn't work 😟 I saw the simberian simulation for pam-4 at 70Ghz but I was wondering if there's a physical sfp test fixture to measure the interconnect in the real world. Like an Sfp sized board with SMA connectors that you could connect DTDR to, and look at impedance through your connector to other end and see RL and IL?
There is one company that makes an adapter for high-Gbps SFP connectors. Check out Wilder Technologies. The module provides coax outputs so you can connect to a VNA for differential S-parameter measurements of the RX and TX pairs. When you connect it to your board you will have to de-embed the transmission line, so I'm not sure how you would do that with this test adapter.
Hi Zach, Thankyou for the info. Actually I was having some doubts regarding the SFP routing. In the SFP pins, I have often seen that, for the differential signal pad's references are given on fourth or below layer instead of the verry near reference layer. In some cases, voids are provided below these pads. Could you please comment about this practice?
Can any MAC interface work? do those PHY chips use MII ot RMII or some other protocol ? Also regarding the Switch project will it be entirely modernized or just a SFP added ? Also will you release the files?
MAC and PHY layers are rated for certain data rates, and the PHY will only support certain routing, so you need to make sure the interface on the fiber module is compatible with the pins on your PHY. For example, SFP-10GM-T from FS supports SGMII, so your PHY would also need to support SGMII. Older Ethernet controllers still support these protocols. Or for example, if you build the chipset in an FPGA, you would instantiate specific MAC & PHY as IP in the FPGA, and the interface for your required data rate would get specific pin grouping on the device.
How did he drag the connector into the cage? Altium won't let me place overlapping components :(
This was a dummy board so there was not a special rule to set (as far as I recall)... I don't know if there is a setting in the Preferences that would limit this overlap, but I regularly place the cage and connector in the same region without problems.
Well how does that work with say AFBR-5972BZ? I guess it's basically like a SFP but doesn't need have the extra cages stuff.
Similar usage in that they have Rx and Tx lanes but does not need the cage like you say. Fiber can plug directly into the coupler end of these transceivers.
Thanks very much for this timely video. I am looking forward to the video where you update a legacy design to use SFPs. Any idea when this is going to be published? Also, would you be willing to share the origin of the layout you presented in your video so I can take a closer look (time 9:23 in video)?
Great timing! I'm working on a 25GBase card and ... First rev doesn't work 😟
I saw the simberian simulation for pam-4 at 70Ghz but I was wondering if there's a physical sfp test fixture to measure the interconnect in the real world. Like an Sfp sized board with SMA connectors that you could connect DTDR to, and look at impedance through your connector to other end and see RL and IL?
There is one company that makes an adapter for high-Gbps SFP connectors. Check out Wilder Technologies. The module provides coax outputs so you can connect to a VNA for differential S-parameter measurements of the RX and TX pairs. When you connect it to your board you will have to de-embed the transmission line, so I'm not sure how you would do that with this test adapter.
@@Zachariah-Peterson @Zachariah Peterson This is exactly what I was thinking of, thanks!
Hi Zach,
Thankyou for the info. Actually I was having some doubts regarding the SFP routing. In the SFP pins, I have often seen that, for the differential signal pad's references are given on fourth or below layer instead of the verry near reference layer. In some cases, voids are provided below these pads. Could you please comment about this practice?
So many subjects and tips, great pace of video's! Thanks Zach / Altium
One topic I'm kinda struggling with RN is getting reliable pcie signalling through a slot to a card edge connector for an add in card
What exactly is the problem? What PCIe generation is it?
Can any MAC interface work? do those PHY chips use MII ot RMII or some other protocol ?
Also regarding the Switch project will it be entirely modernized or just a SFP added ?
Also will you release the files?
MAC and PHY layers are rated for certain data rates, and the PHY will only support certain routing, so you need to make sure the interface on the fiber module is compatible with the pins on your PHY. For example, SFP-10GM-T from FS supports SGMII, so your PHY would also need to support SGMII. Older Ethernet controllers still support these protocols. Or for example, if you build the chipset in an FPGA, you would instantiate specific MAC & PHY as IP in the FPGA, and the interface for your required data rate would get specific pin grouping on the device.