ZYNQ AXI Interfaces Part 2 (Lesson 4)
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- เผยแพร่เมื่อ 28 ส.ค. 2024
- The Xilinx ZYNQ Training Video-Book, will contain a series of Videos through which we will make the audience familiar with the architecture of the ZYNQ device. Then, we will teach how one can design embedded systems for the ZYNQ using the Vivado environment.
this is something even with money you cant buy such good quality tutorial thanks a lot
Very detailed and well explained. I've been looking for these kinds of hand-on detailed tutorials all over. Thanks. Looking forward to the next lesson.
You are a genius! I have been looking for videos of this quality for a long time. Thank you for making them public and free to use!
These videos are a great contribution. Thank you very much!
huge thanks, Dr. Sadri for publishing these great tutorials
Really Really Really Excellent. Not many people have the willingness ti share their knowledge. Let alone with such good quality.
سلام جناب صدری.... دست شما درد نکنه واقعا عالی بود... انشالله هرجا هستید موفق و سلامت باشید
Awesome! Thanks for a great tutorial :-)
I expect more videos to learn more about my Zynq system.
Nice job.
Thank you!
We just uploaded the next Lesson here: th-cam.com/video/sl8xCMu39Mk/w-d-xo.html it will be available in some minutes.
Regards
Thank You for your Effort , These videos save me a lot of time and gave better Insights for working on my Minized Zynq Board
wow the video series is on point, thank you very much for the course!
Great Tutorial ! Very detailed and easy to follow. Keep up the good work.
veri cool stuff. Thank you very much for your efforts and greetings to TU KL !
Excellent walk through, very helpful.
Very helpful explanation , thank you so much 👍
Great tutorial. Thanks!
thanks for the video
Thank you for the great videos.
These videos are great! I have been using them to fill gaps of knowledge after the FPGA/SOC courses I took in college.
Probably a noob question but: what's the advantage in using a separate terminal if the Vivado/SDK GUIs can do the same tasks without a separate program?
I would be interested as well
You are the best!
thanks, Dr. Sadr
Thanks Sadri. This is a great video to start with. It involves many concept that beginners should know. I would like to know how to port through windows OS? I am quite new to this platform. Thanks.
Another question: The block design verilog wrappe rhas those DDR and FIXED_IO signals. But in the previous lesson, the ZYNQ diagram did not show these signals being routed out from the FPGA to the system. The only connection it showed was through the HPx ports to DDR and the GPx through interconnects. Did I miss anything?
This may be a dumb question, but with other tools that I have used, I have seen the need to explicitly write to the UART address space in order to get it to print to the console via UART. Do the functions used xio.h automatically do this? I would have assumed that the functions would send the messages over the JTAG connection. Any insight would be much appreciated.
Thank you very much :)
What are necessary steps to do the same task (which you have explain in this lesson 4 i.e. read-write to BRAM) over Linux application running on PS? Is there any Xilinx document which explain this?
Could this also have been done using a single AXI Interconnect with two slave inputs and two master outputs?
I wish he covered the installation of Unumbuto (Linux).
Mohammad, You can make an udev rule to keep track of your ttyUSBX. I have this in my /etc/udev/rules.d/91-zed-usb-serial.rules
ACTION=="add", ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="0008", ATTRS{serial}=="044301C42216", SYMLINK+="zedboard",MODE="666", GROUP="uucp"
This way I can connect to the serial port as /dev/zedboard. I'm using kermit so the group owner is uucp, which you might have to change. Of course you have to make the vendor, product, and serial match your board as well. You will probably want to use a different name as well... I do the same thing with my Altera board as well. Again, thank you for a great tutorial.
Why you don't use the same ax_mem_interconnect with two channel of M_AXI and S_AXI ? why you use two axi_mem_interconnect ? thanks
Can I ask for the zynq-7000 series that all organize such wiring, right? (I am a newbie)
The adresses were were changed from
0x40000000 - 0x40001FFF
0x40002000 - 0x40003FFF
to
0x40000000 - 0x40001FFF
0x80000000 - 0x80001FFF
why not
0x40000000 - 0x7FFFFFFF
0x80000000 - 0xBFFFFFFF
like in the table? Was this on purpose or an error and it just worked by chance?
What happens actually if we don't change the address of bram_ctrl_1 from 0x40002000 to 0x800000000? Do we get some kind of error or Vivado would let that happen?
Great job sir ! could you explain me why i get this error ? I'm on Vivado 2016.4.
ERROR: [BD 41-1075] Cannot create address segment for in at 0x40002000 [ 8K ]. The proposed address exceeds the base address limitations of the interface(s) through which this peripheral is accessed by this address space
ERROR: [BD 5-48] Error: running assign_bd_address.
I would appreciate if you answer this problem.
Running this TCL script seemed to do the trick. Must be a Vivado bug.
TCL:
create_bd_addr_seg -range 0x2000 -offset 0x80000000 [get_bd_addr_spaces /processing_system7_0/Data] [get_bd_addr_segs {/axi_bram_ctrl_1/S_AXI/Mem0}] SEG0
I also encountered with the same error message however while you go to the Address Editor in the Vivado, you will find that your "axi_bram_ctrl_1" is Unmapped; so you should give the Specific Address to the Unmapped "axi_bram_ctrl_1" which is 0x80000000 in the given case (address for the GP1). And I think after mapping the address you should be able to go further.
in vivado you can not "give" a specific address in the address editor. The vivado is not alowing to edit or input a new address by hand
Better solution: Right click the not included piece. Select include. Right click select assign. Change to correct address
His example still fails at synthesis following instructions 1 for 1 with the edit for accepting BRAM 0x8000_... for GP1 access. Vivado 2022.2.2 attempt on Zybo Z710
How could one apply SDC Constraints on Zynq PL Portion any lecture mentions that? I Request information.
A very helpful and well explained tutorial!!! I have a rather silly question, in the program, we didn't configure the data in the address of GP0 (0x40000000) to be copied to the address of GP1 (0x80000000), why is it when we read from address 0x80000000, the data appeared to be the data in address of 0x40000000? Thank you!
Hello Kin, if you look at the block diagram of our design you can see that we are using one single block memory with two ports and each of these two ports is connected to a separate axi bram controller. one of the axi bram controllers is accessible through gp0 and another one through gp1. so practically GP0 and GP1 are sharing one single unique block memory. this is why you see a same data.
thank you so much...it makes more sense now!!!a very good series of tutorial!!!keep it up!hopefully tosee more video coming
Thank you
Hello Mohammad, What is the procedure to carry out same exercise on board that is not listed while creating vivado project?
So you have a ZYNQ board which is not listed by default in Vivado when you want to begin a project. Then the first thing I would look for is if there exists any board definition file for my specific board. If yes, I go ahead and just add the new board definition so that I can have it in the list of available boards in vivado. (for example look here: zedboard.org/content/board-definition-files-0) If there is no board definition file, then you may like to create one for your specific board and use it since then ( look here : forums.xilinx.com/t5/3rd-Party-Other-Boards-and-Kits/How-to-create-a-board-definition-file/td-p/339025)
Well, finally you can also forget about board definition files completely and directly go ahead by selecting your zynq target device when creating the project. Here you need to take care of all of the required configuration parameters of the PS. e.g. the parameters related to the DRAM controller. Or the ones who define which peripheral is enabled and which one not.
Dear Dr. Sadri,
If I have multiple BRAMs connected in my design and i want to connect them in the ARM host, How will I do it considering there are only 2 GP0, GP1 ports
Did you get an answer? I have the same doubt.
i constantly get an error 'Can not access FPGA space: level shifters are not enabled". As you have told in this lesson, i have put ps7_post_config() routine in main. FPGA is also getting programmed before i dow application. what could be going wrong?
Hi. well, If you are sure that ps7_post_config is executed but level shifters are still not enabled, you can do it yourself manually. Look at the ZYNQ TRM document, at the end there is an appendix which lists all of the registers, there you find the register responsible for changing the state of level shifters, the register is in locked mode by default, you should first unlock it, then make level shifters active and then lock it back again.
Said that, I believe you are not running the ps7_post_config, probably it is located some where which is not being executed. Or your elf is running before the fpga fabric configuration gets done!
Where can i buy the zynq dev boards?
hi mohammad when i folow your method the data read from bram comes like lifo i mean if i put AABBCCDD then it comes as DDCCBBAA why do u think is it happening??
Well, for example if with XMD I write aabbccdd to the bram I expect to read back the same thing. But if you are writing to the BRAM from some where within the PL, and then
reading it back at ARM side then probably what you are seeing is related to the fact that the ARM subsystem is little endian.
[BD 41-1075] Cannot create address segment for in at 0x40002000 [ 8K ]. The proposed address exceeds the base address limitations of the interface(s) through which this peripheral is accessed by this address space
I am getting this error while I created GP1 port in ZYNQ then run the "connection automation" to connect this GP1 to "axi_bram_ctrl_1". And, also axi_bram_ctrl_1 is unmapped in "Address editor".
Thank you in advance.
Try creating the address segment in Tcl Console
create_bd_addr_seg -range 0x10000 -offset 0x80000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_bram_ctrl_1/S_AXI/Mem0] SEG1
where do i get those 32-bit libraries/packages ? what is it called ?
Hello,
for 32 bit libraries,
for old version of ubuntu, e.g. 10.. you can use this command
apt-get install ia32-libs
and for newer versions e.g. 14...
it will be a procedure using these commands :
sudo dpkg --add-architecture i386
sudo apt-get update
sudo apt-get install libc6:i386 libncurses5:i386 libstdc++6:i386
Best Regards
Thanks a lot