Hi All, thanks for your interest in another one of my videos! I was reminded on reddit to emphasise that the AW and W channel can both be written to at the same time, you don't need to write the address first and then the data. I do discuss it in more detail in part 2, but I realise the diagram here shows address before data, and that doesn't have to be the case.
Hi Stacey, great video, thank you. The only thing I think you should have mentioned is that the transactions diagram you shown at (0:09) is relating to AXI-full, not AXI-lite protocol.
Stream interfaces are confusing: They say video is a stream, hence one should use stream DMA to transfer it, but i understand video as sequence of 2D frames. Each frame needs a buffer, it can't just leak as a sequence, so I think it should be memory-mapped...
Hi Stacey, thank you so much for your videos. These are very helpful :) One quick question, so ultimately these AXI4-Lite interface essentially consists of multiple AXI streaming interfaces correct? Is that the right way to think about this? Essentially AXI Streaming interface is a building block for AXI4-Lite?
I would appreciate if you did an spi_slave design using sclk as the clock edge. I know you would have to use block ram or a FIFO for handling a cross clock domain to the rest of the system. I rarely see this approach handled and would like to see how you would do it. Need is for the slow response time on cross domain clicking the spi cli and already running on slower fpga devices with 50MHz clock. The spi protocol can be very simplistic, very controlled usuage.
Hi All, thanks for your interest in another one of my videos! I was reminded on reddit to emphasise that the AW and W channel can both be written to at the same time, you don't need to write the address first and then the data. I do discuss it in more detail in part 2, but I realise the diagram here shows address before data, and that doesn't have to be the case.
Thanks a lot!
I love how data sounds like daughter, makes the video even more interesting :D
Wow, this is super helpful, you really simplified it down, thanks!
You are wonderful!! This space is so underserviced, I am inspired and learning so much from contributors like you.
Thank you so much. This really helps boil it down to an easily digestable format.
Thanks was searching for a comprehensive example on it for a long time.
Thank you for making it a bit easier to get into hardware design
She's back! ~ 💖💖💖
Good to see you back :)
Thank you for taking the time to make these!
Thanks a lot for the video Stacey
Thanks Stacey, keep making video for us.
Thanks for the video! Keep up the good content💖
Great video! Do you have a video about your way of documenting verilog code by chance?)
Hi Stacey, great video, thank you. The only thing I think you should have mentioned is that the transactions diagram you shown at (0:09) is relating to AXI-full, not AXI-lite protocol.
This was really great.
Quite insightful 😀😀😀😀
😚😚😍😍🤍 Thanks for all videos , but please could you illustration the DMA and FFT (radixes 4) algorithm?
I learned a lot from this video.
thank you very much. ^_^
You're welcome!
Stream interfaces are confusing: They say video is a stream, hence one should use stream DMA to transfer it, but i understand video as sequence of 2D frames. Each frame needs a buffer, it can't just leak as a sequence, so I think it should be memory-mapped...
Hi Stacey, thank you so much for your videos. These are very helpful :) One quick question, so ultimately these AXI4-Lite interface essentially consists of multiple AXI streaming interfaces correct? Is that the right way to think about this? Essentially AXI Streaming interface is a building block for AXI4-Lite?
how to build a axi4lite sram controller from this code can u give a tutorial
I would appreciate if you did an spi_slave design using sclk as the clock edge. I know you would have to use block ram or a FIFO for handling a cross clock domain to the rest of the system. I rarely see this approach handled and would like to see how you would do it. Need is for the slow response time on cross domain clicking the spi cli and already running on slower fpga devices with 50MHz clock. The spi protocol can be very simplistic, very controlled usuage.
where is tb for axi lite design?
Hi! thanks for the video. Is there any way to us to reach that documents. Thanks
It's called the the AXI4 specification
www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf