How to solve design challenges on interfacing Ethernet PHY with processors or microcontrollers
ฝัง
- เผยแพร่เมื่อ 3 มิ.ย. 2019
- Download the industrial gigabit Ethernet PHY reference design
www.ti.com/tool/TIDA-010010
This video shows how to solve design challenges on interfacing Ethernet PHY
with application processors or microcontrollers. It covers the fundamentals
of Ethernet design, provides an example based on a TI reference design that
integrates the Sitara™ AM5728 processor and the DP83867 Gigabit Ethernet
PHY and provides an overview of other TI solutions that can be used to
resolve Ethernet PHY design challenges. - วิทยาศาสตร์และเทคโนโลยี
Thanks, this just made my job a whole lot easier
At the start of the video, RGMII was described as it takes 125MHz Clock freq whereas later we were designing with a clock input of 25MHz, I just got confused. is there anything I missed, Thanks
Hello this clock is usually generated internally from the 25Mhz clock (probably from a PLL) or accepted from an external source (Such as a MAC) as a125MHz signal input signal.
19:34: for what are the "magnetics"?
They're isolation components. Ethernet spec requires galvanic isolation from the cable. They're often built into the RJ45 jack. There's a blurry image at 4:10, but RJ45 jack data sheets (like the HY931147C) have more readable schematics.
RGMII has 4 tx and 4 Rx lines