Noah De Los Santos
Noah De Los Santos
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Go to visit CSEP and check out their research programs:
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Vivado Tutorial: Turn Verilog IP into AXI Module
มุมมอง 6K3 ปีที่แล้ว
This video describes an overview of how I converted my Verilog IP into an AXI module in Vivado so I could test my design. I am currently testing with a PYNQ Z1 board so results may vary if you are working with a different board. If you have any questions, leave them in the comment section and I will try to answer them to the best of my abilities.

ความคิดเห็น

  • @stevenalexander6262
    @stevenalexander6262 7 วันที่ผ่านมา

    very nice, AXI is so new to me and I just wanted to use my newly made verilog code on my pynq, this helped tons

  • @MonishaK-sh9bk
    @MonishaK-sh9bk 4 หลายเดือนก่อน

    i want to know how to give my data into the IP, using SDK , please provide any video or documents

  • @weiyizhang4317
    @weiyizhang4317 2 ปีที่แล้ว

    Hello, thank you for the lesson very much! I wonder is there any example which uses both input and output axi stream? Thanks a lot!

  • @iremnurcolak620
    @iremnurcolak620 3 ปีที่แล้ว

    Hello, what is IP? I was looking for AXI implementation but I came across IP in TH-cam a lot. I do not know what it is actually. Thanks :)

    • @clintlemire8741
      @clintlemire8741 7 หลายเดือนก่อน

      Intellectual Property. In this context, it is referring to your design.

  • @mriosrivas
    @mriosrivas 3 ปีที่แล้ว

    This is what I was looking for. Thank you so much, I really appreciate your effort!

  • @beccadls2838
    @beccadls2838 3 ปีที่แล้ว

    Pop off king

  • @kirtikumarbaba
    @kirtikumarbaba 3 ปีที่แล้ว

    it's useful thanks.!

  • @beccadls2838
    @beccadls2838 4 ปีที่แล้ว

    Didn’t understand a word of this but cool!