Then we need to use handshake based pulse synchronizer , so that multiple pulse won't cause metastability ,yup there is delay definitely , we have to consider this delay while design
@Karthik Vippala can u pls explain what happens if after metastability the value is settled to "0" not 1? u can explain with respect to handshake or regular toggle/pulse synchronizer.
Hi Karthik, great explanation, quick silly question: why did you use an xor gate in toggle based synchronizer to convert a level to pulse but an and and gate in handshake based pulse synchronizer to do the same? Thank you
Sir, what will be the total delay between the input pulse and the final state where finally the system will release the busy signal. Because then, this will become the actual delay between the input and output impulse right?
How 0 in left mux will be able to send it to FA1, since second has mux has control condition sinput? Only condition is when busy signal is used at that moment, it should stop the propagation of sinput ie controlling condition of second mux as (BUSY & SINPUT)
When we use xor even when FB2q is low we will get a pulse which is not expected , we use AND gate and not so that whenever FB2q is high we will get a pulse only at that time . Hope this clears your doubt 👍
See at we use xor then , we will get a pulse at starting ie when fb2 is high and fb3 is low , and also at ending when fb2 is low and when fb3 is high So prefering and gate and inverter we will get pulse only once Hope this clears your doubt if you have any doubts please feel free to comment 👍
Hey pulkit , thanks for asking the question, Please check out the playlist on synchronization it might be helpful for you to find other ways . Good luck 👍
this is not going to work if clk A is much slower than clk B. Imagine "sinput" is still high by the time a level returns from domain B to domain A. The second mux is not going to catch it until "sinput" goes low
Namaste , yeah this is will not work for the case u mentioned. Hello sir, can we have a discussion on youtube , about vlsi , will be helpful for audience . Thanks for commenting, Good luck & Great health.:)
Hy, That was a great explanation. I just had a doubt whether the busy signal should be OR gated? Because if Qa is high ACK would still be high and that's a false true condition. (Because it is still synchronizing first pusle) I guess ACK= QA2+ (~QA). Correct me of i am wrong
@karthik vippala I too have this doubt. If this diagram that you have mentioned in the video is right, Busy signal can become zero if either qa3 or qa1 becomes 0 ?
@@saiprasadszhayi where is the mistake? This is a busy signal. when the output of QA1 is high, then busy has to 1 only. I didn't understand you. Can you explain me what is your question.
Very effective teaching
You are just fabulous😀
Namaskaram Ankush , you too are fabulous :) thanks for the support, good luck and great health .
Very excellent explanation...thank u so much
Any more topic suggestion for videos 👍
@@KarthikVippala u explained about pulse based synchronisation... what if multiple pulses are there..how to synchronise them
Then we need to use handshake based pulse synchronizer , so that multiple pulse won't cause metastability ,yup there is delay definitely , we have to consider this delay while design
Recirculation mux synchronisation
@@uday5786do you mean muxed base synchronizer
This is just great channel mate!
Thank you mate! Good luck, good health 👍😊
Great explanation
Thank you 🙏
@Karthik Vippala can u pls explain what happens if after metastability the value is settled to "0" not 1? u can explain with respect to handshake or regular toggle/pulse synchronizer.
thanks a lot. very helpful.
Your welcome, good luck, good health 👍
Hi Karthik, I have only one question how to select s_input to mux that you shown in diagram
Hi Karthik, great explanation, quick silly question: why did you use an xor gate in toggle based synchronizer to convert a level to pulse but an and and gate in handshake based pulse synchronizer to do the same? Thank you
May be it was in the book, I was referring🤖
Sir, what will be the total delay between the input pulse and the final state where finally the system will release the busy signal. Because then, this will become the actual delay between the input and output impulse right?
What if we are not generating the data from FSM but getting it from some microcontroller where we can't control the data?
How 0 in left mux will be able to send it to FA1, since second has mux has control condition sinput?
Only condition is when busy signal is used at that moment, it should stop the propagation of sinput ie controlling condition of second mux as (BUSY & SINPUT)
When converting from level to pulse after synchronisation why can’t we use XOR gate to convert it to pulse?
should I say or will u analyze?👍
Please explain
When we use xor even when FB2q is low we will get a pulse which is not expected , we use AND gate and not so that whenever FB2q is high we will get a pulse only at that time .
Hope this clears your doubt 👍
Anyway we are doing XOR of fb2 and fb3. fb3 is delayed by one clock cycle . So I think XOR also does the same if I am wrong can u explain in detail
See at we use xor then , we will get a pulse at starting ie when fb2 is high and fb3 is low , and also at ending when fb2 is low and when fb3 is high
So prefering and gate and inverter we will get pulse only once
Hope this clears your doubt if you have any doubts please feel free to comment 👍
How it's convert from pulse to level. Can you elaborate this point what is this means.
Namaskaram Shubham 🙏,Please check in my channel , you can find pulse to level video .
Good luck & great health👍😀
is it used for high to low and low to high freq both?
Hey Rajeev , thanks for asking, Yes we can use it for both.
Good luck, good health 👍
which synchronizer is used if frequency is same but its asynchronous clock?
Please check out synchronizer playlist on my channel 👍
Any other way for pulse synch? Or this is unique well known implementation?
Hey pulkit , thanks for asking the question,
Please check out the playlist on synchronization it might be helpful for you to find other ways .
Good luck 👍
can u draw the timing diagram for next input too ???
Namaste gangotri 🙏 , if you're stuck anywhere I can help you .
Good luck & great health 👍😊
It's handshake pulse based right...can u do on handshake synchronization..
Ok I'll do it by next week Tuesday 👍
this is not going to work if clk A is much slower than clk B. Imagine "sinput" is still high by the time a level returns from domain B to domain A. The second mux is not going to catch it until "sinput" goes low
Namaste , yeah this is will not work for the case u mentioned.
Hello sir, can we have a discussion on youtube , about vlsi , will be helpful for audience .
Thanks for commenting, Good luck & Great health.:)
Hy,
That was a great explanation.
I just had a doubt whether the busy signal should be OR gated?
Because if Qa is high ACK would still be high and that's a false true condition. (Because it is still synchronizing first pusle)
I guess ACK= QA2+ (~QA). Correct me of i am wrong
Hey sai prasad ,can you be clear about Qa 1 or 2 ?
Thanks for asking, good luck, good health 👍😊
@@KarthikVippala QA1 output of FA1 and QA3 output of FA3.
ACK = (~QA1) + QA3
@karthik vippala I too have this doubt. If this diagram that you have mentioned in the video is right, Busy signal can become zero if either qa3 or qa1 becomes 0 ?
@@sharanyagopalan1717 it's an or gate
@@saiprasadszhayi where is the mistake? This is a busy signal. when the output of QA1 is high, then busy has to 1 only. I didn't understand you. Can you explain me what is your question.
sync out output is not used any where in further.
Namaskaram jyotsana 🙏, sync out will be used in design , that's shown only for reference , good luck & great health 👍😊