There was a point made about using the pull-ups in sd-cards or similar disconnectable devices... especially on miso and cs lines to avoid leaving them floating or subject to noise when connected.
@InTimeTraveller it's good practice not to leave any inputs floating (miso floats when no slave is selected). Esd hazard, noise making input stage to switch at random, half-way voltage that means undetermined state which "half opens" the cmos, etc... (Microcontrollers manufacturers advise not to leave unused pins as high-z inputs, but to config them as low outputs for the same reasons). I think most modern spi chips have internal pullup/down on input pins, but I am not sure.
@robegatt ESD is not going to be dissipated by a pull up/pull down resistor, you need TVS diodes for that or other specific ESD mitigation strategies. The rest is really unnecessary unless you have a safety critical system. In other words, all noise is gonna do is just have a random initial state of the system. It is therefore at best unnecessary for the vast majority of applications and at worst it increases BOM and layout size, and adds a constant power draw which may or may not be important depending on the application. Otherwise by the same logic you might as well add PU/PD resistors to all your IO lines and then suddenly the BOM is getting ridiculous.
@InTimeTraveller No. The clamping of the ESD is usually done internally with diodes, the electrostatic charges couple with the gate capacitance and charge the gate at random, ALWAYS, not just at the beginning (where did you get this idea of noise only at the beginning anyway?!). If you have a pullupdown you have a reference voltage with known amount of charges. The floating input is like a small antenna and gets a continously changing state of the input buffer that generates noise on the power delivery network due to the switching. If the cmos gates are in linear zone both transistors are letting some current through dissipating unnecessary power. Why do you think microcontrollers ALWAYS have configurable pullups (and or pulldowns) on their gpio input stages ? just to avoid cluttering the layout and the bom. That is why I think modern spi interfaces have internal pullups.
As an ASIC engineer I can tell you that if your IC vendor tells you "pulls" are needed, then you should use them. With CMOS inputs you should not leave the pin state at an intermediate level, the pin should either be fully "on" or fully "off", otherwise you end up with potentially significant crossbar currents. The need for "pulls" really are for inputs or inouts (when they are in input mode). Typical ASIC IO libraries have a large selection of IO buffer types for the ASIC team to choose from (or of course they could use a custom IO design). As an ASIC designer I can choose to use input capable buffers that have "no pulls", "pull up" or "pull down" or in some libraries the ability to configure them. For designs reasons that are beyond this discussion the designer may choose to use an input buffer that has no "internal pulls", in this case the local PCB design is required to ensure that the input pins does not float and has a valid input level at all times. A PCB pull resistor does this. However, in the other case where the chip designers has used input buffers with pulls it is a little more complicated, many input buffers that include pulls have one important caveat. They are not to be used to replace the need for "board level" pull resistors. They internal pulls are very weak and intended to ensure the input buffer has a valid input level only when the pin is left disconnected. The behavioural simulation models often even include huge delays in modelling the pulls to avoid designers relying in them. IMHO it is why there seems to be "no consistency" in where SPI connections need pulls or not, in part is is because what other functionality is shared on those pins, can they be configured as inputs, might they be used for undisclosed test or "secret" functionality etc? If you want the definitive answer as to whether a pin requires a pull resistor, ask the chip vendor/designer and follow their advice because they actually know if and why they would be required.
@@roowatt interesting... the internal pulls HAVE to be weak also because otherwise in a parallel connection you cannot go from strong to weak...only viceversa.
Most of the time just follow whatever your chip manufacturer suggests. Recently i worked with a PCIE to SPI bridge that required pull ups on some of the SPI lines and would just not work without it.
Have you done any videos on ground reference resistors and bias resistors in analog circuits? I know how to do the maths for these, but today's digital kiddies might benefit from one of your deep dives on the subject.
I have come to the conclusion that the pull-ups are mostly useful to have a well defined initial state for the SPI bus. This could also be useful for any other pins that are not SPI, but where you want a guaranteed initial state, e.g. one that controls a transistor base/gate or relay. Like you said, for most stateless ICs (like a sensor) this initial state doesn't matter. If the undefined state of the bus magically sends a valid but unknown SPI command, I'm probably just gonna send a reset command to the device during initialization. You didn't touch on the resistor seen between SI and SO signals. That could be useful when interfacing between 3-wire simplex and 4-wire duplex SPI interfaces, though I've never actually done that.
This is exactly it. Even on the example Zach showed with the TPS65987DDk, a pullup on the MISO line (called SPI_POCI on TI chip) is needed to configure the part to automatically read in configuration data from SPI flash on boot vs another mode. It has nothing to do with the actual operation of SPI
Many micros boot with their GPIOs defaulting to inputs until the code has a chance to configure them. Therefore the pullup resistor ensures no spurious chip selects or clocks before the processor has a chance to start
In my opinion, you need resistance for pullups when can do 10+ reps. My simulations for Zach's arms in AWR show that resistance does not work him anymore because he can do 100+ reps. If I add a short ended transmission line and set his pullup frequency right, it will have high reactive impedance and make his workouts challenging, allowing him to progress.
There was a point made about using the pull-ups in sd-cards or similar disconnectable devices... especially on miso and cs lines to avoid leaving them floating or subject to noise when connected.
For CS it makes sense, but in MISO it really doesn't. As long as the CS is deasserted it really makes no difference what the MISO does or doesn't do.
@InTimeTraveller it's good practice not to leave any inputs floating (miso floats when no slave is selected). Esd hazard, noise making input stage to switch at random, half-way voltage that means undetermined state which "half opens" the cmos, etc... (Microcontrollers manufacturers advise not to leave unused pins as high-z inputs, but to config them as low outputs for the same reasons).
I think most modern spi chips have internal pullup/down on input pins, but I am not sure.
@robegatt ESD is not going to be dissipated by a pull up/pull down resistor, you need TVS diodes for that or other specific ESD mitigation strategies. The rest is really unnecessary unless you have a safety critical system. In other words, all noise is gonna do is just have a random initial state of the system. It is therefore at best unnecessary for the vast majority of applications and at worst it increases BOM and layout size, and adds a constant power draw which may or may not be important depending on the application. Otherwise by the same logic you might as well add PU/PD resistors to all your IO lines and then suddenly the BOM is getting ridiculous.
@InTimeTraveller No. The clamping of the ESD is usually done internally with diodes, the electrostatic charges couple with the gate capacitance and charge the gate at random, ALWAYS, not just at the beginning (where did you get this idea of noise only at the beginning anyway?!). If you have a pullupdown you have a reference voltage with known amount of charges.
The floating input is like a small antenna and gets a continously changing state of the input buffer that generates noise on the power delivery network due to the switching.
If the cmos gates are in linear zone both transistors are letting some current through dissipating unnecessary power.
Why do you think microcontrollers ALWAYS have configurable pullups (and or pulldowns) on their gpio input stages ? just to avoid cluttering the layout and the bom. That is why I think modern spi interfaces have internal pullups.
As an ASIC engineer I can tell you that if your IC vendor tells you "pulls" are needed, then you should use them. With CMOS inputs you should not leave the pin state at an intermediate level, the pin should either be fully "on" or fully "off", otherwise you end up with potentially significant crossbar currents.
The need for "pulls" really are for inputs or inouts (when they are in input mode). Typical ASIC IO libraries have a large selection of IO buffer types for the ASIC team to choose from (or of course they could use a custom IO design). As an ASIC designer I can choose to use input capable buffers that have "no pulls", "pull up" or "pull down" or in some libraries the ability to configure them.
For designs reasons that are beyond this discussion the designer may choose to use an input buffer that has no "internal pulls", in this case the local PCB design is required to ensure that the input pins does not float and has a valid input level at all times. A PCB pull resistor does this.
However, in the other case where the chip designers has used input buffers with pulls it is a little more complicated, many input buffers that include pulls have one important caveat. They are not to be used to replace the need for "board level" pull resistors. They internal pulls are very weak and intended to ensure the input buffer has a valid input level only when the pin is left disconnected. The behavioural simulation models often even include huge delays in modelling the pulls to avoid designers relying in them.
IMHO it is why there seems to be "no consistency" in where SPI connections need pulls or not, in part is is because what other functionality is shared on those pins, can they be configured as inputs, might they be used for undisclosed test or "secret" functionality etc?
If you want the definitive answer as to whether a pin requires a pull resistor, ask the chip vendor/designer and follow their advice because they actually know if and why they would be required.
@@roowatt interesting... the internal pulls HAVE to be weak also because otherwise in a parallel connection you cannot go from strong to weak...only viceversa.
Most of the time just follow whatever your chip manufacturer suggests. Recently i worked with a PCIE to SPI bridge that required pull ups on some of the SPI lines and would just not work without it.
Hopefully that is now the case for modern chips, but there are a lot of legacy datasheets that preach gospel that has been refuted experimentally.
Why does the mfg say that it needs pull ups on SPI lines? Does it have an open drain output or sth?
Have you done any videos on ground reference resistors and bias resistors in analog circuits? I know how to do the maths for these, but today's digital kiddies might benefit from one of your deep dives on the subject.
I have come to the conclusion that the pull-ups are mostly useful to have a well defined initial state for the SPI bus. This could also be useful for any other pins that are not SPI, but where you want a guaranteed initial state, e.g. one that controls a transistor base/gate or relay.
Like you said, for most stateless ICs (like a sensor) this initial state doesn't matter. If the undefined state of the bus magically sends a valid but unknown SPI command, I'm probably just gonna send a reset command to the device during initialization.
You didn't touch on the resistor seen between SI and SO signals. That could be useful when interfacing between 3-wire simplex and 4-wire duplex SPI interfaces, though I've never actually done that.
Some spi connections support half duplex 3 wire, that's the way you connect them.
This is exactly it. Even on the example Zach showed with the TPS65987DDk, a pullup on the MISO line (called SPI_POCI on TI chip) is needed to configure the part to automatically read in configuration data from SPI flash on boot vs another mode. It has nothing to do with the actual operation of SPI
thank you very much Zach,
not only teaching smth fruitful but also opening my mind on thinking about circuits.
Many micros boot with their GPIOs defaulting to inputs until the code has a chance to configure them. Therefore the pullup resistor ensures no spurious chip selects or clocks before the processor has a chance to start
Zach, how to contact you by E-mail? I would like to attach some files and explanation of my problem with Altium? Thanks in advance!
In my opinion, you need resistance for pullups when can do 10+ reps. My simulations for Zach's arms in AWR show that resistance does not work him anymore because he can do 100+ reps. If I add a short ended transmission line and set his pullup frequency right, it will have high reactive impedance and make his workouts challenging, allowing him to progress.
Needs a better pdn.
Too much effort for this joke bro.
Everyone knows you only need series ferrite beads for SPI bus signals.
😂