Packaging Part 6 - Wafer to Panel Level Packaging

[@richh9366]

Dr. Navid is treasure. Really enjoy all of his presentations and learn so much.

[@haoxu4328]

Really informative and well-structured presentation! Thank you very much, Pls make more like this!!!!

[@depressivepumpkin7312]

thank you very much for not having a heavy Indian accent, cheers

[@miNIMMAlmovement]

It's Alonso so why would he?

[@ErossaanBooming]

Very Impressive how structured your presentation is :)

[@zhangwisdom5660]

Fan in and Fan Out session, it is pretty good for useful.

[@SK-le1gm]

amazing presentation thank you !!!

[@falconi7633]

On slide WLP Challenges: "Nickel" instead of "Nitrate" for UBM?

[@eima7644]

Make more of this video, please. 3D stacking manufacturing processes and such.

[@MrBubblegumx]

For mold first the carrier wafer is only needed during molding, right? Why does it have to be silicon?

[@jorgekaz07]

Very nice presentation, very informative. Just a small question: pg2 is "badge" supposed to mean "batch"?
Otherwise great video. Thanks for sharing!

[@frederikvanstolk5815]

Why would die shift be a PLP issue more so than a WLP issue? If it's due to CTE mismatch you'd see it happen in WLP as well surely?

[@dylan522p]

Navid confused about your comments on panel level. Intel uses panel substrates from multiple vendors.

[@hgb1696]

What's difference between Cowos and WLP, does foveros and cowos do not pkg on the wafer level?