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Navid Asadi
เข้าร่วมเมื่อ 29 ก.ย. 2011
PAckaging Part 16 2 - Silicon Photonics & Global Indsutry Dynamics
PAckaging Part 16 2 - Silicon Photonics & Global Indsutry Dynamics
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Packaging Part 21 - Thermal Challenges in Advanced Packaging
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Packaging Part 21 - Thermal Challenges in Advanced Packaging
Packaging Part 20 - Package Substrates
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Packaging Part 20 - Package Substrates
Packaging Part 19 - Thermal Measurements in Advanced Packaging
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Packaging Part 19 - Thermal Measurements in Advanced Packaging
Packaging Part 18 - Memory Devices Packaging and Challenges
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Packaging Part 18 - Memory Devices Packaging and Challenges
Packaging Part 15 1 - Nanoelectromechanical Systems(NEMS) Devices
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Packaging Part 15 1 - Nanoelectromechanical Systems(NEMS) Devices
Packaging Part 16 1 - Overview of Silicon Photonics
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Packaging Part 16 1 - Overview of Silicon Photonics
Packaging Part 15 2 - Packaging for MEMS Devices
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Packaging Part 15 2 - Packaging for MEMS Devices
Packaging Part 13 - Antenna in Package (AiP)
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Packaging Part 13 - Antenna in Package (AiP)
SCAN Lab Tour - LINK TO THE LAB VR TOUR IN THE DESCRIPION
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Link to SCAN lab VR Tour: my.matterport.com/show/?m=YVWh646Zp5L List of the equipment in video 1. Zeiss ORION NANOFAB 2. HAMAMATSU PHEMOS-1000 3. Bruker SKYSCAN 2211 4. TESCA FERA 5. TESCAN LYRA 6. PROTEMICS TERACUBE 7. IMINA IN_SITU NANOPROBING 8. ZEISS STEMI 9. ALLIED XPREP
Packaging Part 11 - HI Integrated Circuit Co Design
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Packaging Part 11 - HI Integrated Circuit Co Design
Packaging Part 16 3 - Integrated Silicon Photonics
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Packaging Part 16 3 - Integrated Silicon Photonics
Packaging Part 10 - Heterogeneous Integration Materials
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Packaging Part 10 - Heterogeneous Integration Materials
Packaging part 9 - Heterogeneous Integration Interconnections
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Packaging part 9 - Heterogeneous Integration Interconnections
IC Assurance - Intelligent Physical Inspection for Counterfeit IC Detection
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IC Assurance - Intelligent Physical Inspection for Counterfeit IC Detection
Packaging Part 8 - Failure Analysis for IC Packaging
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Packaging Part 8 - Failure Analysis for IC Packaging
Acoustic Imaging for Electronics Assurance
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Acoustic Imaging for Electronics Assurance
Packaging Part 5 - Manufacturing process
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Packaging Part 5 - Manufacturing process
Packaging Part 6 - Wafer to Panel Level Packaging
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Packaging Part 6 - Wafer to Panel Level Packaging
Excellent rundown! Ty.
great presentation, do you have the slides that can be shared?
No Mr Die, I want you to Bond
Is SiP the transition technology to achieving SoC so far? or is is a way better solution than SoC?
IDM
Very Informative lectuer thank Prof Navid !
Well done, Navid!
不错
On slide WLP Challenges: "Nickel" instead of "Nitrate" for UBM?
nice! thank you
For mold first the carrier wafer is only needed during molding, right? Why does it have to be silicon?
correction no. 2: (15:35) - there are sockets for BGA;
Motorola 68020 has PGA package from 1984
Please share your contact details Please
Things that I can learn for one month it takes five years since 2019.
Now computer design tools actually integrate all of these domains 9:26 kind of their own in the background. My algorithm is doing that configuration through 'Logical optimization'.
Stacking of ICs one above other in layers connecting them together.
very good lecture
Take a look at entire series
Thank you very much☺
Amazing video !
سلام و احترام جناب اسدی.ممنون از آموزشهای بسیار خوب شما. جناب اسدس من دانشجوی ارشد فوتونیک در ایران هستم و دنیال یک مثال آماده nonlinear micro ring resonator هستم.آیا شما چنین مثال آماده ای که با FDTD شبیه سازی شده باشد دارید؟ یا منبع و پایگاهی سراغ دارید که دانشجویان فایلهای شبیه سازی شان را به اشتراک بگذارند؟
reading peed is too fast to follow
I can't wait for engineers to start writing software in a form that can be read by these systems, so we'll finally have software and hardware unified.
Thanks for the comprehensive overview!
Daniel, Nice overview Please consider a takeaway statement at the bottom to highlight your conclusive intent 1,000 points
awesome lecture, thank you!
What can you say about durability, long lifespan of Power management IC units in Chiplet
When will we get 2nm with chiplet packaging
When will we get 2nm with chiplet packaging
Is it possible to get the slide deck?
good video 🙏 but it's awkward for a package substrate introduction video, ABF is not mentioned at all....
all big and great company in the world😮
Very informative
Great video!
سلام و احترام جناب اسدی. امکان راهنمایی و کمک در انجام پایانامه رشته فوتونیک وجود داره برای شما؟
Many thanks.
Thanks a lot Dr. ❤
Great video, seems like you put the same section once, when talking about thermal reflectance microscopy, please check it out, thanks!
the clearest explanation for interposer. I have been confused for a long time.
Well done. Now understand what an interposer is. Thanks!!
Very interesting and good to know to learn 3D packaging for beginner! Thanks to share
Very useful keep making videos
greater power, more thermal issues😀
Dr. Navid is treasure. Really enjoy all of his presentations and learn so much.
In 1992 Motorola designed and created 1200 pin CBGA's for the PCB's on the Iridium payload.
Thank you so much for these videos. Easily the best I have seen in my 8 years in the industry.
These presentations are very good, but sadly RUINED by constant advertising every few minutes.
Hello can I get your presentation file?
Thank you
Great video! 👍 thank you!
You're missing Lightwave Logic under the Design listing