Another fantastic video, brother. You could charge for access to your stuff, but instead you provide it to us for free. I hope you can share more information like this. Thank you! Humans such as yourselves revive my faith in mankind.
As a practicing PCB designer and EE, this video is a fantastic example showcasing many important concepts used by high-speed designers. Very well done mate!
Phil, definitely you are making an invaluable job, thank you for your efforts, for support, I'll immediately buy your course about this content when it is ready. I would love to see how we can customize the timings of the custom DDR in petalinux.
Missed the patreon meetup as I dont think i actually have any 'use' for this knowledge, but I absolutely love learning it anyway (if things in life health wise ended differently I may have been able to graduate my Elec Eng degree and be doing this stuff etc.. but alas it didnt work out that way). Again can't wait for your course cause even though I have no use for it, it'll still be awesome to learn it!!!!
Nice video! I recently bought a few Zynq 015 chips which have 4 MGT transceivers, and I intend to make a board with a PCIE x4 slot on it. I already have a premade MyIR board with 015 and a PCIE, but it's only has two lanes wired up, but I already tried many PCIE extensions cards - among them was NVME SSD (via PCIE-to-M.2 adapter), 2.5G Ethernet card, USB 3.0 card - basically all extension cards I had laying around, and once I enabled drivers for these devices, they all worked (well, with 2.5G Ethernet it was a bit more involved because it required a firmware to run). My initial idea was to place a PCIE switch so that I can connect both NVME SSD and some other external card at the same time, but these switches are very expensive (PEX8612 is about 70$ per device!), so I decided to ditch that idea for now. I also have a few of Zynq 030's with Kintex fabric and 10G MGTs which I hope to find a use for some day.
Thanks! Sounds like you have some cool projects & ideas lined up. I'd like to give the Zynq Ultrascale parts a try on a custom board this year (if time allows) - as you said, trying to find a use right now is another thing..
I distinctly recall my uni professor saying external memory won't ever go faster than 64 MHz because of PCB constraints. So apparently what you're doing here is not possible :)
Thanks! Luckily for Xilinx, they've made PetaLinux which sits on top of Yocto, so one doesn't have to deal as much with the nitty gritties.. In any case, that's definitely my least-favourite part of this bring-up :D
Hi, Thanks for your content, could you tell me please if the DDR shared between PL and PS in FPGA Zynq? did you manage to connect the DDR to SoC only ?
Hi Phil. All your series are amazing, both here and in the Altium channel. I have only one question : How many hours did it take for you to design the schematic and the PCB of this dev board ? Thanks a lot for your contents
This ZettBrett series has been great-- more info on using DDR memory is always good, I always find DDR mystifying. Will be cool to see Linux running on the board. Maybe even see you build your own distro with Yocto? :D Joking, but will be curious to see you getting the RTL8211 PHY and I2C/SPI working under Linux.
Hi, thanks a lot for the video. 1. Where can I found the internal delay of the Zynq chip? 2. How can I import in Altium project? 3. Did you do a video with the constrains to use for DDR routing? Thanks again.
Great video! One thing is clear, you can't program an SoC with a DIY toolchain like we do with small MCUs, I can only image how much software there is behind vivado and vitis to make all that flawlessly work. Where did you learned all this? Official xilinx docs and application notes?
Thanks! I believe some people have been working on open-source toolchains for Xilinx parts, but I haven't been following that closely. Xilinx docs/app notes are actually pretty decent IMO, so those & just making projects is how I learned this.
I am using Altium 23.2.1 and have watched many of your videos and they are very useful. I also work with an FPGA Designer that handles the VITUS and Vivado side of the design and these videos help me understand the design from that perspective. I am working on several boards with different Zynq parts (the Big Ones). I have several designs that are candidates for Reuse. One of the components in this Reuses opportunity exists over 8 schematic sheets. This FPGA has 23 different parts (heterogenous part- BIG Zynq). Should I go through the multiple schematic pages selecting all the relevant components and signals all at one time creating the Reuse Block and then do the same thing with the PCB design? Or should I copy all 23 sheets of my schematic pages and make one giant schematic sheet (size J?) and make that a reuse block? How can I handle this situation? Can I make the whole design a Reuse Block as it is (23 schematic sheets) Or make one giant schematic sheet and make that a Reuse Block? Thanks for your TH-cam Channel!
Great video, as always ;) if you encounter any problems with Linux, building u-boot, kernel, dtb or the rootfs feel free to msg me, I'll be more than happy to help ;)
You've been on fire the last few months. I am adding you to my recommended channels list.
you're videos are awesome as well man, its been a while
Thank you very much - awesome to hear that you've been following the channel!
Highly technical and complex engineering concepts explained nicely and clearly. Well done!
Another fantastic video, brother. You could charge for access to your stuff, but instead you provide it to us for free. I hope you can share more information like this. Thank you! Humans such as yourselves revive my faith in mankind.
Thank you very much, Alexandros! Definitely many more videos to come :)
As a practicing PCB designer and EE, this video is a fantastic example showcasing many important concepts used by high-speed designers. Very well done mate!
Thank you very much, Rio!
Phil, definitely you are making an invaluable job, thank you for your efforts, for support, I'll immediately buy your course about this content when it is ready.
I would love to see how we can customize the timings of the custom DDR in petalinux.
Excellent and fully covered video for DDR on bring up. Each step is detailed very deeply. Thanks indeed :)
Missed the patreon meetup as I dont think i actually have any 'use' for this knowledge, but I absolutely love learning it anyway (if things in life health wise ended differently I may have been able to graduate my Elec Eng degree and be doing this stuff etc.. but alas it didnt work out that way).
Again can't wait for your course cause even though I have no use for it, it'll still be awesome to learn it!!!!
Nice video! I recently bought a few Zynq 015 chips which have 4 MGT transceivers, and I intend to make a board with a PCIE x4 slot on it. I already have a premade MyIR board with 015 and a PCIE, but it's only has two lanes wired up, but I already tried many PCIE extensions cards - among them was NVME SSD (via PCIE-to-M.2 adapter), 2.5G Ethernet card, USB 3.0 card - basically all extension cards I had laying around, and once I enabled drivers for these devices, they all worked (well, with 2.5G Ethernet it was a bit more involved because it required a firmware to run). My initial idea was to place a PCIE switch so that I can connect both NVME SSD and some other external card at the same time, but these switches are very expensive (PEX8612 is about 70$ per device!), so I decided to ditch that idea for now. I also have a few of Zynq 030's with Kintex fabric and 10G MGTs which I hope to find a use for some day.
Thanks! Sounds like you have some cool projects & ideas lined up. I'd like to give the Zynq Ultrascale parts a try on a custom board this year (if time allows) - as you said, trying to find a use right now is another thing..
@@PhilsLab Yeah, I've been itching to try the UltraScale+ parts (not just Zynq, but FPGAs as well), but they are just too damn expensive for me.
Fantastic content as always!
I distinctly recall my uni professor saying external memory won't ever go faster than 64 MHz because of PCB constraints. So apparently what you're doing here is not possible :)
Haha must be magic then!
Great explanation!
Thank you!
Nice! :)
Been trying to get yocto Linux up and running on an Intel based SBC recently. Interesting to see how you get Linux up and running!
Thanks! Luckily for Xilinx, they've made PetaLinux which sits on top of Yocto, so one doesn't have to deal as much with the nitty gritties.. In any case, that's definitely my least-favourite part of this bring-up :D
So good videos, keep going on 👍
Thanks, Rodrigo!
Thank you, youre great!
Hi, Thanks for your content, could you tell me please if the DDR shared between PL and PS in FPGA Zynq? did you manage to connect the DDR to SoC only ?
Sir please upload lecture on hardware design of this board.
Hi Phil.
All your series are amazing, both here and in the Altium channel.
I have only one question : How many hours did it take for you to design the schematic and the PCB of this dev board ?
Thanks a lot for your contents
This ZettBrett series has been great-- more info on using DDR memory is always good, I always find DDR mystifying. Will be cool to see Linux running on the board. Maybe even see you build your own distro with Yocto? :D Joking, but will be curious to see you getting the RTL8211 PHY and I2C/SPI working under Linux.
Doesn't he do that in part 5?
Hi, thanks a lot for the video. 1. Where can I found the internal delay of the Zynq chip? 2. How can I import in Altium project? 3. Did you do a video with the constrains to use for DDR routing? Thanks again.
Great video! One thing is clear, you can't program an SoC with a DIY toolchain like we do with small MCUs, I can only image how much software there is behind vivado and vitis to make all that flawlessly work. Where did you learned all this? Official xilinx docs and application notes?
Thanks! I believe some people have been working on open-source toolchains for Xilinx parts, but I haven't been following that closely. Xilinx docs/app notes are actually pretty decent IMO, so those & just making projects is how I learned this.
I am using Altium 23.2.1 and have watched many of your videos and they are very useful. I also work with an FPGA Designer that handles the VITUS and Vivado side of the design and these videos help me understand the design from that perspective. I am working on several boards with different Zynq parts (the Big Ones). I have several designs that are candidates for Reuse. One of the components in this Reuses opportunity exists over 8 schematic sheets. This FPGA has 23 different parts (heterogenous part- BIG Zynq). Should I go through the multiple schematic pages selecting all the relevant components and signals all at one time creating the Reuse Block and then do the same thing with the PCB design? Or should I copy all 23 sheets of my schematic pages and make one giant schematic sheet (size J?) and make that a reuse block? How can I handle this situation? Can I make the whole design a Reuse Block as it is (23 schematic sheets) Or make one giant schematic sheet and make that a Reuse Block? Thanks for your TH-cam Channel!
There is one small issue finding the FPGA
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Great video, as always ;) if you encounter any problems with Linux, building u-boot, kernel, dtb or the rootfs feel free to msg me, I'll be more than happy to help ;)
DdR3. Sucks rename ddr name