How to Do DDR Memory Bit & Byte Swapping - DDR2, DDR3, DDR4, ....
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- เผยแพร่เมื่อ 10 ก.พ. 2021
- Do you know what a nibble in DDR memory design is?
Links:
- iMX6 DDR3 Design Guide: www.fedevel.com/welldoneblog/...
- DDR4 Layout Design PDF: www.nxp.com/files-static/32bi...
- DDR Commands PDF: www.samsung.com/semiconductor...
- DDR Mirroring: welldoneblog.fedevel.com/2011...
- Memory Module PDF: www.compuram.biz/documents/da...
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It is much appreciated. Thank you,
- Robert
Robert is an expert sharing his knowledge that he gained throughout the years, thank you for that!
Thank you A Z
Very useful stuff. I like PCB design and after I saw your videos I started to like it even more. Your channel is a true oasis of information for PCB designers :)
A next great content! Completely new field for me but learned a lot. You inspired me to start more complicated boards! Thank you!
Robert, your timing is more than excellent - myself working acutally specifically on a LPDDR4-project. Huge thank you from my side and both thumbs up for this video! ;-)
I am really glad that this kind of quality information is available on the internet for free, credit to you Robert, I am sure your techniques and suggestions have influenced many people in their decision making during designs. Also just wanted to mention one thing on the X4 DDR configuration especially on DIMMs, I had this question and found this answer. DRAMs are generally used in x4 configuration to increase the density (mostly in DIMMs), for example, if we take 512Mb DRAM device and if we use in X16 config, we can only use 4 of them (for 64 bit) so the density is 2Gb, but if we use the same DRAM in X4 config, we can use 16 of them (for 64 bit) so the density will be 8Gb.
This is useful tip to make our pcb layout much more easy
Golden! This is very good content, thank you Robert.
I am doing a ddr4 project with im8m now! Amazing help robert! Thank you
Wow, you have a great way of teaching, thank you!
You are one of my favorite youtubers. Love this quality content!! I have to buy a shirt to support your great work sir.
thank you
I've been having broblems with STM32 + SDRAM pinout. As always, you uploaded the video just in the right moment to rescue me from headache :D
Thank you Bence
Very good video. For me, the most complicated thing is to put the rules of distances between lane signals, between signals of different lanes, between strobe and lane, clock, etc. And then the exceptions below the BGA. A video on this topic would be fantastic!
I just came online and saw this.. the last I saw of this was in a PDF and it was very cryptic & impossible to understand.. THANK YOU SIR for sharing your experience with us. ♥️
Thank you Ekenedilichukwu Ekeh
Hi Robert... Happy to see a nice informative video on DDR4...I closely follow your videos..Plz make a video on High Speed PCB Design(JESD204B based) where in DAC,ADC and SoC all are in same board. Just needed some advice with respect to these type of boards.Thanks
Another Great Useful video as Usual , Thanks for sharing your knowledge Sir, Your are inspiration for me and many peoples
Thank you very much Haribabu
Good note on address swapping. I always presumed it was ok to swap them, but might cause less predictable performance on sequential accesses due to additional column/row select latency. I had forgotten that DDR doesn't have a separate command bus.
Thanks Robert! I will try to retain this info in my human memory 😉
Excellent. Thank you for sharing your knowledge.
Thank you Siddharth for leaving your feedback
Really good one.
Very useful, thanks.
I find Altium's pin swapping feature is really useful for this. Just set up the byte lane groups to let Altium know which pins in which bytes groups can be swapped in the schematic side, enable pin swapping for the component of interest and in PCB side use the automatic pin swap optimiser. Also the interactive pin swapping tool is useful in cases where the automatic one doesn't give swaps that are suitable or you want to manually swap. And then you update the schematics from the PCB side (the reverse of the usual SCH to PCB update).
Thank you Kalhana. I do not know if they improved this feature, but when I was testing it couple of years ago I didn't like leaving Altium doing any changes in my schematic. So, I just like to swap it manually and having full control over every change in schematic.
@@RobertFeranec Yes I was also a bit paranoid about it messing up the schematics. But it was very useful for me for LPDDR4 routing as well as for mapping FPGA pins (because FPGA pins are very flexible within the banks with same I/O voltage etc.).
The setting I use is "Adding/Removing Net-Labels" in the "Project Settings"->Options"->"Allow Pin-Swapping Using These Methods". And Altium will swap the net labels near the IC. The other tick box will actually change the pins of the symbols which I don't like. I think it's a very powerful feature.
Thank you!
I love these videos
Thank you Olaf
I remember when I also swapped address lines for SRAM memory chips. This is possible.
But then I did the same for SDRAM which is fatally wrong as you explained at the end of your video.
It was very disappointing... But life goes on...
SUPER!
Another great video!
I'm still having issues routing DDR busses. I'mdoing something wrong for sure!
About data pin swapping Once I received a development board that was having issues with the EMMC, I've then discovered that by mistake they swapped two data pins.
Unfortunatly The EMMC bus was also used for the SD card so thet was broken too. (it was working fine on the same broken HW but across devices it was not working for obvious reasons.)
Thank you TuttoCrafting
best conntent!
Good video Robert! So according to NXP DDR4 Layout Design guide bit-swapping is only allowed within a nibble in one data bank in DDR4. Will it be working if I swap bits within a whole data bank in DDR4 interface the same way like in DDR3?
Very nice
Thank you Prasad
Assolutamente!! the one ! (;=))
Hello Robert Feranec,
First of all, thanks for your great work!
I would like to use a 400MHz uP to access 4 DDR4 memories, is it possible?
Or will I run into difficulties with speed limitations that prevent it from working?
I would like to know if you are available to collaborate on a brief work.
Great Video! I had no idea about the requirement of the lsb, or the restriction for nibble swapping. However, wouldn't the nibble swapping constraint only apply to DIMMs? It looks like it arises to support x4 chips, however, if you are using x8 or x16 chips, then it wouldn't apply, right?
Luckily, DDR is much more forgiving with bit / byte swapping, unlike LPDDR (which can be a pain to route as a result). Although, I would be curious for your opinion on the memory type / topology for single board solutions (i.e. not DIMMs). Specifically, I am thinking in the context of FPGAs where swapping can be even more forgiving than with SoCs.
Some specific questions:
1) If the routing constraint is eased, is there a reason to choose for example LPDDR2/3 over DDR3? My thought would be that LPDDR would be easier to ensure that there aren't any electrical issues for a given capacity, since it's point-to-point.
2) Is there a reason to use narrower chips other than capacity? i.e. four DDR3x8 vs two DDR3x16?
3) Are there benefits to different topology types for multiple chips? i.e. if you have two DDR3x16 chips, is it better to route them in a T-toplogy, or a fly-by topology? Or is the main consideration there board area?
Thank you hjups. PS: I am 100% sure, but nibbles may be important also if you use ECC(?) 1) We usually choose based on application 2) In my opinion, no - we always select base on available space and required maximum capacity 3) T-topology has limit in max frequency (?) ... I have not tested this, but I have only seen T-branch up to 533MHz, anything above was always fly-by
@@RobertFeranec I thought ECC was implemented as a 9th byte? It's been a while since I looked at it though.
(1) so if either LPDDR2 or DDR3 would work for an application, would you opt to go with LPDDR2 because it's point-to-point? Or would you still opt for DDR3?
(3) Interesting, I didn't realize that T had that limitation - my only experience is with single chips that are 400 MHz or less (FPGA applications), so I wasn't sure. In such applications where the speed is lower, are there any reasons to choose T over flyby? I guess T would be a lower BoM cost because it doesn't need termination. Though thinking about it, I think the layout requirements for Xilinx are that the address/command lines go between data groups, so that would imply a required T topology (otherwise fanout would be harder).
Hello hjups! I almost had a heart attack when i read your comment about LPDDR bit/byte swapping disability, because my recent project used LPDDR :) I didn't know this information about LPDDR. I started to read forums/topics, i tried to find JESD209A (unsuccessful).
The only thing i found is "Because LPDDR2 devices (both DRAM and NVM) assign specific functions to the different byte lanes of the data bus and even to specific bits within the bytes, byte and bit swapping shall be avoided". It's only for LPDDR2.
Hello Robert,
When we do byte-swapping between two memory chips, won't this generate an error on the processor side because the read/write operation was intended for a memory ship but it was performed on another memory chip?
You can only bit/byte swap on any individual chip. It might not generate an error unless you are trying to load and execute code from the memory, but it would certainly result in corruption.
Now this type of videos cannot be condensed to < 10 minutes...
:)
I don't think I heard you mention it, but bit/nibble/byte swapping should a second step for DDR interface optimization. Proper layout should be first. On the SoC side, the upper and lower nibbles should be vaguely grouped, and DQS should be somewhere in the middle.
When you bring the vias down to lower layers, it should be done in a way that keeps these bundles together. The vias in the design referenced here seem to not be placed in any kind of pattern or grid which is one of the reasons why such extreme DQ swapping is used here.
Most designs (I mainly deal with x86 to be fair) should be fine with swapping within nibbles at most.
Here's an old DDR3 down design guide from Intel www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-system-memory-down-paper.pdf. If you zoom in on the figures in Page17-21, you see that the vias are grouped and ordered well, making routing easier.
NXP does similar but it's just hard to see here (Figure 7 & 8) www.nxp.com/docs/en/application-note/AN2582.pdf
Thank you Kev
Can someone explain why it is so important for the (byte wise) least significant bit of the data bus to always connect to the least significant bit on the memory?
Unless it is used as part of a command, I can't quite figure out why this should matter at all?!
The traces are so close to one another, and the things works in GHz frequencies. What about crosstalk? How do you counter it there? Also, is it good or bad or doesn't matter to have ground pours between traces?
I hope it's okay I try to answer? :-)
Robert has made several fantastic videos about exactly that subject but in general shall you place a ground plane, right under the signal plane and do everything you can to never cut or place tacks on a ground plane. To minimize cross talk do you do best in trying to keep minimum 4 × H distance between tracks (H = vertical distance to ground plane from signal track).
@@friedmule5403 thank you, I will search through Robert's videos for more detail then!
@@ilyas.7209 You are so welcome! :-)
Great idea, he has so much fantastic information, and most of it is surprising!! I.e. the copper tracks are NOT where the signal/energy is traveling. :-)
I cant find your sharing on the internet 😢😢