Working of Edge-Triggered D Flip Flop
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- เผยแพร่เมื่อ 2 ต.ค. 2024
- The D-type flip-flop or Data Latch has only one input referred to as the “D”, or data input, plus a clock input, CLK along with the usual two outputs, Q and Q. The D-type flip-flop transfers its digital data between the input and its outputs, after a delay of one clock pulse and so the “D” part is also referred to as a “delay” input.
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I used headphones to listen and heard your breath sound showing how much nervous you are but appreciate you for your well-defined and best lecture ❤
The one thing that I think this video missed was, what happens on the falling edge of the clock signal? I worked it through myself and it looks like the output would remain the same. Other than that, very helpful thank you
Yes, true. If a flip flop is positive edge triggered, then input will be effective only on the rising edge of clock, and there will be no change on falling edge. For negative edge triggered flip flop, output will be changed on the falling edge of the clock signal and no change at the rising edge.
very clear explanation , thankyou mam
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How did do you decide which output of NAND gate to compute first and pass it to next NAND gate? Because the sequence of choosing NAND gate is changing the outcome
Because we are starting with the minimum information and NAND gate is the only gate whose output can be predicted with this min info.
Very very nice explanation !!!!
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Very very nice explanation !!!!
thank u