Behaviour of Master Slave D Flip Flop
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- เผยแพร่เมื่อ 21 ก.ย. 2024
- Digital Electronics: Behavior of Master Slave D Flip Flop
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I never seen someone doing such a hardwork for free.. thank you sir,
Yeah, sush
Kabhi physics walla ka naam suna hai ?
They're getting paid by TH-cam!
@@saadajaz7972 maa ki chuuu uski
You are doing really great work which will not be in vain.
My explanation...
D = Direct change
Qm = Master output
Qs = Slave output
Qp = Master output, only changes when triggered on the Positive-edge
Qn = Slave output, only changes when triggered on the Negative-edge
The clock is used as the enable for Qm and Qp.
The inverted clock is used as the enable for Qs and Qn.
When clock is 1, Qm will be the same as D. Qs will remain unchanged.
When a clock changes from 0 to 1, Qp will be the same as D. Qn will remain unchanged.
When the clock is 0, Qs will be the same as D. Qm will remain unchanged.
When a clock changes from 1 to 0, Qn will be the same as D. Qp will remain unchanged.
the difference between my class teacher and you is...i feel sleepy and headache when my teacher giving lecture..but i feel fresh happy and wish to see your whole lecture continue....love you alot sir...thank you so much for all your did..
I fell asleep while watching this video. It still helped me understand the concept tho, it was a good video.
I had been struggling about this topic for a long time, and did not understand anything.. But now EVERYTHİNG IS CLEAR THANKS TO YOUR VIDEOS. Thank you so much sir, may God bless you.
D = Direct change
Qm = Master output
Qs = Slave output
Qp = Master output, only changes when triggered on the Positive-edge
Qn = Slave output, only changes when triggered on the Negative-edge
The clock is used as the enable for Qm and Qp.
The inverted clock is used as the enable for Qs and Qn.
When clock is 1, Qm will be the same as D. Qs will remain unchanged.
When a clock changes from 0 to 1, Qp will be the same as D. Qn will remain unchanged.
When the clock is 0, Qs will be the same as D. Qm will remain unchanged.
When a clock changes from 1 to 0, Qn will be the same as D. Qp will remain unchanged (copied)
you don't explain graphs well
No doubt sir...
All the doubts are at one side and your explanation is at another side 👍👍👍😊😊😊
A crores of thanks from me🙏🙏🙏🙏🙏🙏🙏🙏
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions.
Your lectures are great.
Thank you so much for them.
Outstanding video. Thank you very much!
If there is a word more than a perfect it deserves u a lot. Such a clarity and patience I wonder really how u developed!!!! Seriously speechless sir.... We r really blessed by God. Thanks.keep rocking all d best sir. Hope all ur dreams come true in the upcoming future
What a great knowledge, I pray to be like you Sir in Electronics World.
Thank you very much and Remain Blessed!
very much helpful and the fact that the videos are of maximum 15 minutes makes it very much learning. I used to fear from Digital Logic Design ,n after watching your video i am able to understand the concept very well.
I have a confusion between Qm and Qp. Both are D FFs but they produce different waveforms that is the first one is level triggered while the second one is edge triggered.
Anyways great video.
that is what exactly i was tried to comment.
Because the Qp one is for the whole flip flop. But Qm is the only for the master part of this which acts like a latch.
Cause master slave is generally used for level triggered flip flop
Because one is level triggered and other edge triggered
D = Direct change
Qm = Master output
Qs = Slave output
Qp = Master output, only changes when triggered on the Positive-edge
Qn = Slave output, only changes when triggered on the Negative-edge
The clock is used as the enable for Qm and Qp.
The inverted clock is used as the enable for Qs and Qn.
When clock is 1, Qm will be the same as D. Qs will remain unchanged.
When a clock changes from 0 to 1, Qp will be the same as D. Qn will remain unchanged.
When the clock is 0, Qs will be the same as D. Qm will remain unchanged.
When a clock changes from 1 to 0, Qn will be the same as D. Qp will remain unchanged.
no words, each and every word is important ....flow of explanation is mind blowing
It would be nice if you gave explanation of certain facts as well as cause-reason connections. What I mean, is sometimes it’s not clear why truth tables are written as they are. E.g. when clock is active it means it orders data to be memorised, and when inactive, any data can pass through. I hope I have explained my point well. Thank you again for your work! ❤️
Thanks for this u answered my question well
And is there any other resource about this indepth functioning as you said above
The easy way to remember is that the output (Qs) is whatever D was when clock went down (1 to 0). Else, remains same.
very very very thankyou, all are very helpful for me 🧡🧡
love from Bangladesh 💚
you make me so happy .thanks again
you are realy a good teacher .
You Teach In More Informative Way Than My Teacher. Great Man, I Have Paper Tomorrow, I Think It Won't Be Difficult For Me After Watching This... Again Thanks Man
how did it go?
That was brilliant. I love you!
Fantastic - so many concepts in a short video. Thank you.
It has been most amazing lecture I have seen on master slave flip flop
Difference between you and my prof is you can understand it simply solving an example.
Sir in your previous D-FF video you said that it works like a level triggered FF, but here from the graph we see that it is working as -ve edge trigg FF...can you explain this
So much hardworking done by you for explaining and for making diagram.......
keep doing
. sir don't say thanks for watching. WE SHOULD THANK YOU FOR THE LECTURES. YOU ARE INSPIRATION FOR MANY. THANKS FOR THE AMAZING LECTURE SERIES.
Throughout my semester I have seen your videos and it is very very helpful....
I will request you to make a lecture series on Analog Communication Technique...
Thank you very much...
I love when he says if we have any problems to comment below
master: for the +ve part of the clock Qm follows D as it is, and in the -ve part of the clock Qm remains previous state.
slave: for the -ve part of the clock Qs follows Qm as it is, and +ve part of the clock Qs remains previous state.
It was a very good lecture. Thanks a lot.
Qm: (high)level triggered o/p of master ff.
Qs: (low) level triggered o/p of slave Ff for input Qm.
Qp,Qs: edge triggered waveform of data input signal.
Sir i have just come out from a boring lecture of digital electronics . I don't want to sit there and waste my time and i am here watching your lectures . Thank you so much sir.
Ans to why Qp and Qm does not give the same o/p.
Here D flip flop is a line triggering flip flop so the o/p changes to a certain level of the clock pulse,we will get Qm according to the i/p that is D,but where as Qp is a edge triggering flip flop.
Question🙏🏾: What's the essence of using master-slave D Flipflop when in "D flip flops", it is impossible to have the two inputs as same. i.e it shouldn't be possible to have input of S=1 and R=1.
Please reply @Neso Academy...I have the same doubt
Watch 10.40 for the reason for using d FF in this configuration
Main Purpose of Master-slave flip is to remove glitches
when you analysis the ff for the output of Qm and Qs it act as alevel sesitive, becz as there is a change in d-ff input the output changed.
But when you do analysis on by considering individual ff you consider the edge triggering.. whyy???
please explain..............................
Thanks! For a positive-edge triggered flip-flop, just invert the clock signal. (So much for the obvious... ;) )
your expaination is very much better than class lectures. really outstanding...
great, I think the for getting positive edge triggered flip flop, the clocks can be reversed. Not gated clock for master flip flop and direct input for slave flip flop.
moral of the story: use a slave to remove your glitches 😂
Very easy teaching also from basic
this is gold
How is the problem of J=1 and K=1 arising in a single input (complemented) D F/F? Because we are not individually giving 1 and 1 as in the case of two inputs for JK or SR. So the "not used" state doesn't occur at all in D flip flop.
Sir, while discussing negative edge triggering, you have checked the value of D at the moment of the trigger and then drawn waveform, now my doubt is what is the output if 'D' changes at the time of trigger?
I learned that dff reacts to clock changing (and just that clock moment when it goes up)
and there is latch dff which passing d to q as long as he have logical 1 in the clk
in this video, it seems you working with latch dff
i think you should write it in description because it might confuse people
besides that. awsome video and awsome explain
you really helping! thank you.
There is nothing latch FF. Latch can be converted to FF by different methods. Like using master-slave design presented here. Here two latches are used to design FF. Most importnant one, Latches are level trigger, where FFs are edge triggered.
Simplest and best explanation, hats off man!!
this is D Latch no D flip flop as in the D flip flop the signal can you change once during a positive till negative edge triger
Qm cannot go high until the next clock edge. Master is behaving as level triggered latch and not flip flop as you are saying. Can you make correction in this video?
Your explanation is fantastic,you can upload more videos
Why does D flip flop correspond to positive edges?
great lecture sir
whether the clock is edge triggered or level triggered?
you used leve triggering for the master slave flip flop and edge triggering for the simple flip flop right?
thank you so much sir! this video totally save me!!
really appreciable work thanks man
It seems like the master d flip flop is level as well as edge sensitive ! Is that even possible?
I'm also so confused. I dunno. I've always thougt that all flipflops are only trigger sensitive.
@@karlziegmarabuda9125 yeah
Hello Sir, when u do the timing waveform, can u please also introduce some timing parameters, such as setup time, hold time and propagation delay? My textbook mentioned this a bit, but I would like to know more details about this, thank you!
Very straightforward and well explained.... Gracias
Thankyou for useful content
Great video thank you sir!!
Liked, subscribed, and shared with friends. Beautifully demonstrated and summarized. You are a wonderful asset to students!
You are saving me from backlog 😂
Thankyou sir.
Neso is the best !
this one is marvelous.
ghar bethe taaliyan bajane pe majboor 👏👏
Such a nice and clear explanation.
For D flip flop we don't have two inputs same bcoz one input is inverted to another right, then how could we use as D flip flop as master-slave flip flop
Superb methodology sir keep it up.
Thanks
Really helpful Lectures. Thankyou so much
U deserve more subscribers. Very informative video : )
Good Video lecture sir, I have a doubt in your video of master slave flip flip- Let see in the Qm output- you showed two glitches, the second glitches is dropped down without complete one cycle of clock is it write?. it confused about to me. timing from
4:06 to 5:15
I think because the gap between the changes in d and clock is very less. input signal d is low for a very small time
😘🥰❤💗🥳🤘......... for all digital electronics video u have done . I love this course because hard topic are cleared In easy way .😘
why in drawing Qs we do not consider inverse of the clock ??
anyways gr8 video (y)
What is the difference between Qm and Qp? Why is one level triggered and the other edge triggered?
Sir, whether d ff edge triggered or level. Why the d ff used in ms ff is level triggerd when d ff is edge triggered
if negative edge triggered flip and Master Slave are same then why Master slave is in use ?
In Qm, for 2 clock cycle, the Qm should not raise right??
Because, the D flipflop is a edge triggered one, It changes, only during the edge raising and continues till the end of the clock cycle. Please correct me, if Iam wrong!
Thank you for your awesome videos.
VERY NICE
Qm is level triggered so it should be a latch right?Why is it called a flip flop ?Someone please explain
Can anyone plz explain why sir didnot considered the glitches in slave flip flop
Excellent!
Sir, please provide these lectures in a order.initially they are in order but as I go further in the presentations their order is random.
Really videos are the best sir ,I am doing verliog and system verilog course sir, I needed the basic of this digital ones your videos are very worth and very beneficial sir .I have one doubt sir is glitches and race around condition are same sir??
Thank you very much
Thank you so much for this video 😊
Paragliding se jada fun to in lectures me hai 😍
아주 좋아요 ㅎ
Many thank for the good explanation
fantabulous...mind blowing lecture..
Is "Negative Edge Triggered Flip Flop" an abstract idea (which can be achieved by a master-slave flip flop)?
I don't get it why in Qm and QS u used level triggering even though there is a clock and if we have a clock it's suppose to be either + or _ edge triggered ...
Why no glidges formed in negative edge triggered? While Qm has glidges.
Excellent video, thank you so much
Very well explained ❤️
Thanks Sir, its very clear
you did not mention the use of preset and clear in any of your lectures
I want to join hands with neso academy
thank you
Finally understood.Thanks...