𝐋𝐨𝐰 𝐏𝐨𝐰𝐞𝐫 𝐕𝐋𝐒𝐈 𝐃𝐞𝐬𝐢𝐠𝐧 | 𝐃𝐲𝐧𝐚𝐦𝐢𝐜 𝐏𝐨𝐰𝐞𝐫 | 𝐒𝐡𝐨𝐫𝐭 𝐂𝐢𝐫𝐜𝐮𝐢𝐭 𝐏𝐨𝐰𝐞𝐫 | 𝐋𝐞𝐚𝐤𝐚𝐠𝐞 𝐏𝐨𝐰𝐞𝐫 | 𝐏𝐨𝐰𝐞𝐫 𝐎𝐩𝐭𝐢𝐦𝐢𝐳𝐚𝐭𝐢𝐨𝐧 ✅

[@rohanyadala9096]

Very nice..

[@vlsiexcellence]

Thanks @rohanyadala9096

[@shivenpandya8122]

Can you elaborate on how power dissipation is going to impact digital noise directly ?

[@vlsiexcellence]

Thanks @shiven, Power Dissipation will generate Heat, which will cause thermal noise !

[@ramana0070]

Pretty good explanation. Thanks for your effort!!

[@sidstar593]

Is this playlist enough to cover the low power design concepts??

[@vlsiexcellence]

Yes .... it covers all most all the SoC Low Power Design concepts.

[@sidstar593]

@@vlsiexcellence thank you.

[@RandomHubbb]

on slide 16, the clock gating scheme you are showing is glitchy, it should not be used

[@vaishnavich6211]

In dynamic power dissipation formula, since fsw = activity fator * f => Pdynamic = activity factor*C*VDD^2*f......but it is given Pdynamic = activity factor*C*VDD^2*fsw....Is it a typo or am i mistaken somewhere?

[@singhkaptan00]

Thanks for this awesome video.
Doubt:- Sir in most of the textbooks I have read that total power is divided into static and dynamic, whereas dynamic power is further divided into 2 categories:- switching power and short circuit power. But you are referring to the dynamic power as the subcategory of the switching power. Can you please answer me on this? Also, sir the concept you shared at 47:00, is it concept of power gating and are the sleep transistor the power gates?

[@vlsiexcellence]

We can follow the text book nomenclature itself. Just remember that Dynamic/Switching basically represents charging and discharging of circuits node.
For Second Query, Yes. It would work as a Power Switch.
I appreciate your feedback. Thank You
@singhkaptan00

[@panghalmonika08]

Good work Gyan !

[@vlsiexcellence]

Thank you Monika !!

[@singhkaptan00]

Thank you sir for making it so clear.
Sir at 9:19 shouldn't the stored energy be 1/2 CV^2 instead of CV^2 which would dissipate in the Nmos and the internal resistance of the load capacitor

[@vlsiexcellence]

Thats correct ! It would be 1/2 * C*V^2

[@keshavkeshav7]

nice slides

[@vlsiexcellence]

Thank You !! Hope you liked the content.

[@PEC_GauravSingh]

👍👍👍👍👍👍

[@sagarasurendran6365]

sir can you please share these slides?

[@vlsiexcellence]

Sure - github.com/vlsiexcellence/Low-Power-VLSI-Design-LPVLSI

[@debasishkar761]

Please don't use this filling word "nothing but" 😂