Tutorial on low power | clock gating | power gating | level shifter | vlsifab

[@abhishekkumargupta7549]

Nice conceptual video.....Thank you sir.....

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Please share it with your friends too

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[@satyamsingh-xv7wg]

Thanks sir. I am searching for these vedio from long time.

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Please share it in your circle too 🙂

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[@pavan.kumar.muttinenimutti9977]

Thanks bro

[@User--jm5911]

Difference between isolation cells and retention flops??

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[@noopursrivastava843]

Hello sir,
I am facing some issue that I have designed my inverter with io pad as you explained but in this I am getting some property error during lvs. please help me. There is an error in width and length mismatch between layout Vs schematic.
Layout length and width is not in um but schematic length and width is in um.

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[@chethalaramakrishna3959]

Hii sir
What is different between clock gating and icg

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[@Bishnu_Papon]

With in 15 min too much topic are cover

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Did you find it helpful?

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[@Bishnu_Papon]

@@VLSIFaB sure