Design of EX-OR Gate in Verilog Using Xilinx ISE.

[@SayanMondal-yb4hs]

sir can we get the video for xnor gate as well

[@dr.hariprasadnaikbhattu]

Use these statement for XNOR gate:
Gate level model
xnor(Y, A, B);
Data flow model
assign Y = ~(A ^ B);
Procedure is same for all models.

[@smokerji9768]

kindky upload more vedios

[@dr.hariprasadnaikbhattu]

Hi Thanks