Design of NOT, NAND & NOR Gates in Verilog Using Xilinx ISE.

This lab video demonstrates the design of basic logic logic gate using Verilog HDL implemented in Xilinx ISE Simulator.

[@vaibhavmimrot6893]

Bhattu sir you are saving lives

[@dr.hariprasadnaikbhattu]

Thanks 👍

[@gurramsridhar8955]

thank u sir

[@pavaninandan]

Good Morning Sir, Ur Video is very helpful, Can u pls refer website for downloading the software

[@dr.hariprasadnaikbhattu]

Hi
Xilinx 14.5 or 14.7 are outdated.
They can be downloaded from Google search. It is around 6gb

[@mohamedabid7052]

Dear sir, would like your service in order to change a defective Xilinx Virtex 4 processor

[@dr.hariprasadnaikbhattu]

Hi, not much information about it

[@SRIHARSHABHATTU]

Thanks

[@dr.hariprasadnaikbhattu]

Thanks 👍

[@proxxskullxxgaming2955]

Sir I am facing the problem when i was installed the Xilinx software sucessful complete showing but then i will go the Oracle VM manager I click the ISE_14.7_ virtual _ Machine the still process has be starting but A guru mediation errors shows its has been showing a critical error has occurred while running the virtual machine and machine execution has been stopped plzz help me 😭😭 because Monday my final practical exam plzz reply as soon as possible

[@dr.hariprasadnaikbhattu]

Hi, In virtual machine it will be a problem.

[@SauravKumar-kc4wg]

Sir why "simulation terminated" is showing ...and how to rectify this ?

[@dr.hariprasadnaikbhattu]

May be because of software or windows 10

[@SauravKumar-kc4wg]

@@dr.hariprasadnaikbhattu thank you for ur positive response sir ..i have corrected it .

[@qemmm11]

Thanks Sir❤
Create Symbol(Verilog level to level circuits)😊

[@dr.hariprasadnaikbhattu]

Welcome

[@hemallikarjun]

Sir, please share synthesis of RAM