Can we please get more analog design videos on Cadence Virtuoso with explanation. By the way one more favour, can you modify your audio recording in the upcoming videos because you are not quite audible in the videos.
@@amarnathbr3420 I can give you several links from other youtube channels - th-cam.com/video/xk6xNfA8vXc/w-d-xo.html th-cam.com/video/RCGw4hx7nl0/w-d-xo.html
Yes. This is a standard pole equation - w_pole=1/(RC). Since each node of a circuit contributes a pole, you can see ("by inspection") that the node from MOS drain to AC GND has only Rd (or RL) and CL.
very helpful. Thanks a lot. If possible, please post more examples of using the gm/Id method in design. A great example would be an OpAmp or OTA
What software you are using to take notes?
OneNote
תודה רבה דניאל :)
Can we please get more analog design videos on Cadence Virtuoso with explanation.
By the way one more favour, can you modify your audio recording in the upcoming videos because you are not quite audible in the videos.
Thanks @Amarnath for your comment, but unfortunately I do not have time currently to upload more videos :/
@@danielsapir1613 Could you please recommend a website where we can access content on how to make good use of Cadence Virtuoso
@@amarnathbr3420 I can give you several links from other youtube channels - th-cam.com/video/xk6xNfA8vXc/w-d-xo.html
th-cam.com/video/RCGw4hx7nl0/w-d-xo.html
also - cmosedu.com/
@@danielsapir1613 Thank you :)
Can you please let me know why Rd is equal to one over 2pi*f*C?
Yes. This is a standard pole equation - w_pole=1/(RC). Since each node of a circuit contributes a pole, you can see ("by inspection") that the node from MOS drain to AC GND has only Rd (or RL) and CL.
single stage RC ckt Time constant
@@danielsapir1613 thanks :)
volume is way too low