PYNQ example of controlling IP using GPIO

Example of creating an overlay for the using VHDL or Verilog IP, and controlling the IP using GPIO. I.e. the IP does not have an AXI interface.
The HDL is not packaged into IP-XACT format, and is instead added directly to a Vivado IP Integrator project.
www.pynq.io
A Verilog Johnson counter was used from here:
www.myhdl.org/d...
A VHDL clock divider was used from here: allaboutfpga.c...
Please ask questions on the PYNQ support forum: www.pynq.io/sup...

[@kevinnugent8309]

No audio here or is it just me ?

[@imignap]

Thank you for this, got me started! I'm still digesting it without the audio.

[@user-dp7dx6pt1d]

thank you for this! I just start to learn that

[@KRsseds]

One little mistake on Jupyter Notebook Code I guess..
To go to the other direction, you have to do like
left.write(0)
right.write(1)
stop.write(1)
if not, all the bits will stay 1(goLeft, goRight, stop signals) which will result in the maintainance of register 'run' = 1, doing the former function on and on which is goLeft in this case.

[@JanCumps]

For some reason, I had to provide a .hwh file (also created by Vivado instead of the TCL file)
Using PYNQ-Z2 with image 2.6

[@siuchan2449]

I just run the example using PYNQ-Z2 with boot image 2.6. I have the same problem which requires a .hwl file and it seems that they have removed the Tcl parsing in 2.6 according to the change log.

[@JanCumps]

@@siuchan2449 Yes, the good news is that Vivado generates the .hwh file. No blocker, but a change in instructions.

[@DevangsinghSankhala]

4:26 How do you get the GPIO_0 port on the Zynq processing system? I can't find it in my IP customization ...

[@cathalmccabe8618]

If you double click the Zynq PS block, and go to the MIO configuration, you should see I/O peripherals and an option to enable EMIO GPIO. (EMIO connects the PS pins into the PL as opposed to MIO pins which have to be connected to external pins on the chip)

[@melkhoulyihp]

Can I apply the same design on my Ultra96 ?

[@cathalmccabe8618]

Yes! The Ultra96 uses a Zynq Ultrascale, so the IP block will look a little different, but you will have a similar option to enable GPIO, and you can use the GPIO in a similar way from PYNQ. If you have any more detailed questions, you can post them on the PYNQ technical support forum discuss.pynq.io
Cathal

[@diz3344]

​@@cathalmccabe8618 By checking the xdc file of the ultra96 v2 board, I found the package pin of the four user leds, but those four package pins are all read-only, so I cannot set my "led" output port to those package pins. Then how can I place the led into the device?
The package pins of the User LEDs
#set_property PACKAGE_PIN AA3 [get_ports {MIO17_PS_LED3 }]; # "AA3.MIO17_PS_LED3"
#set_property PACKAGE_PIN Y5 [get_ports {MIO18_PS_LED2 }]; # "Y5.MIO18_PS_LED2"
#set_property PACKAGE_PIN AA4 [get_ports {MIO19_PS_LED1 }]; # "AA4.MIO19_PS_LED1"
#set_property PACKAGE_PIN AB4 [get_ports {MIO20_PS_LED0 }]; # "AB4.MIO20_PS_LED0"