Adding IP to a PYNQ overlay - tutorial

Example showing how to add AXI SPI IP to a Vivado IP Integrator design. This design uses the base overlay design for the Pynq-Z1 as a starting point and shows how to modify it and add new IP.
The bitstream is created, along with the block diagram Tcl. the files are copied to the board, and a Python driver can be written for the IP using MMIO.

[@zhengpang4816]

Thanks for this Video...it helps so much

[@raytsang4745]

Thank you so much

[@kevinnugent8309]

No Audio sound or is it just me having this issue ?

[@edwinzapata1626]

No audio :'(

[@galapple1587]

Is there a way to open the base overlay on vivado 2023.1?

[@arunkumarkurapati8093]

Is there another video that continues this one?

[@mohammadmuqseed7995]

yes this doesn't have audio

[@user-mb6cs6rj8p]

this is outdated! For Pynq Z2 I cannot find build_base_ip.tcl on the PYNQ-master downloaded