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Make the algorithm in HLS/C then add to Vivado as IP Design, finish the block then export/generate BitStream to be called in Overlay.
Very helpful and intuitive explanation, thanks a lot
That's very useful, thanks.
11:10 it seems you need the .hwh file as adder.hwh from the hw_handoff subfolder next to the bitstream file on your pynq, otherwise the pynq will show an error message that it cannot locate the bitstream
after generate bitstream, File>Export>Export Hardware then you can get the .xsa file that include the .hwh file
Is it the same if I use this as it is in vitis?
Make the algorithm in HLS/C then add to Vivado as IP Design, finish the block then export/generate BitStream to be called in Overlay.
Very helpful and intuitive explanation, thanks a lot
That's very useful, thanks.
11:10 it seems you need the .hwh file as adder.hwh from the hw_handoff subfolder next to the bitstream file on your pynq, otherwise the pynq will show an error message that it cannot locate the bitstream
after generate bitstream, File>Export>Export Hardware then you can get the .xsa file that include the .hwh file
Is it the same if I use this as it is in vitis?