It seems that the term "bypassing" (wrt write buffer) has two different interpretations: a) load the value from write buffer, thus the load bypasses the global shared memory; b) load the value from the global shared memory, thus the load bypasses the write buffer. It seems this presentation means b), while the book "A primer on memory consistency and cache coherence, 2011" means a).
The speaker used his slot well enough, but this is an hour talk even to properly cover the non-scary state of the sliced onion, with layers peeled off both halves-in strict onion order-by two different sous chefs.
What an amazingly brain-tormenting subject matter. Bulldozer is old news these days, but it just occurred to me that a chip with a pair of bulldozer CMT modules aspects of the load/store model are not even invariant under these rules under permutation of static scheduling. en.wikipedia.org/wiki/File:AMD_Bulldozer_block_diagram_(CPU_core_block).png Check out that mauve "write coalescing cache" block and weep. A pair of threads scheduled to the same CMT might share bypasses from the write buffer, while threads on the other CMT share bypasses on a distinct write buffer. The write buffer sharing domain can be complicated, even inside a single chip! Or maybe the write buffer is implemented inside the LSU and unshared. If so, was it _forced_ to be implemented that way by a memory order specifiation, or could the implementation have chosen to share the write buffer in the next block down?
It seems that the term "bypassing" (wrt write buffer) has two different interpretations: a) load the value from write buffer, thus the load bypasses the global shared memory; b) load the value from the global shared memory, thus the load bypasses the write buffer. It seems this presentation means b), while the book "A primer on memory consistency and cache coherence, 2011" means a).
The speaker used his slot well enough, but this is an hour talk even to properly cover the non-scary state of the sliced onion, with layers peeled off both halves-in strict onion order-by two different sous chefs.
I want the scary version!
Did anyone understand anything?
What an amazingly brain-tormenting subject matter. Bulldozer is old news these days, but it just occurred to me that a chip with a pair of bulldozer CMT modules aspects of the load/store model are not even invariant under these rules under permutation of static scheduling.
en.wikipedia.org/wiki/File:AMD_Bulldozer_block_diagram_(CPU_core_block).png
Check out that mauve "write coalescing cache" block and weep. A pair of threads scheduled to the same CMT might share bypasses from the write buffer, while threads on the other CMT share bypasses on a distinct write buffer. The write buffer sharing domain can be complicated, even inside a single chip! Or maybe the write buffer is implemented inside the LSU and unshared. If so, was it _forced_ to be implemented that way by a memory order specifiation, or could the implementation have chosen to share the write buffer in the next block down?