I am so fortunate to have stumbled across your online resources. I will become a better engineer due to the content that you have produced. Thank you so much!
I just finished the game "Turing Complete" which makes you build a simple computer with 8 bit registers and 32 bit instructions. It's amazing to see similarities between the game's proposed computer architecture and RISC-V. Thank you for the overview.
Just stumbled on this. I haven't worked on hardware for... well.. let's just say I'm not as pretty now as i was back then, but I was able to follow along the entire lecture! Hurray my brain still works! Thanks and I will be looking over your book and your other videos because I'd like to learn more about RISC-V.
Please forgive my confusion. When I heard RISC was doing a Vector chip I assumed that would mean it would have onboard vector graphics libraries for accelerating and simplifying processes similar to Flash, Inkscape, or Processing.js. I would expect a collection of built in libraries of various vector fonts onboard. I was looking forward to being able to make a few simple calls in Assembly and open a window of colorful vector based elipses, arcs, gradients, animated vector text, etc.. When I was an animation student at DeAnza I encouraged a small startup called Macromedia to develop vector animation tools. The idea being one could transmit full screen animations using tiny amounts of data back when 28.8K modems were the norm and bandwidth was dismal. Today microprocessors are the norm. I was picturing handheld devices that can communicate with one another using said scalable graphics and data. We have come full circle where now once again small data is valuable for transmitting between tiny devices. I could go on and on about all the wondrous things one could do. Is that not what this chip is about at all? I am completely baffled! ???
@@dillingerlee2536 The V in RISC-V means 5 in this context... As in version 5. And 'vector' instructions in the context of RISC-V (at the moment) refer to vector registers (a one dimensional array.)
@@JohnsBasement Ah I see! But there is a Vector chip on the near horizon right? I heard folks were already working on an OS for it. If so there should be an emulator for qemu in the near future, yes? Or have I completely got my wires crossed on the topic?
Finally, I've been looking for a simple explanation of risc-v for a long time and this is just what I needed. I'm about to make a RV32I compliant processor in minecraft, so you could use gcc to program it instead of the usual machine code. And if I'm really feeling autistic i could make it RV32G and run fucking linux in minecraft. Very unlikely...
in your latest edition of RISC-V assembly language programing(Draft v0.18.3-0-g8a08bae), in 83rd page where you have combined both description and instruction format of instructions. In the jalr instruction operation description, you have used ^ operator instead of & operator but in 81 page you have given & operator in description. so change ^ operator to &
Ugh.... that is actually correct. the big wedge is a logical AND. I can see that I was, however, inconsistent by using the & on a prior page. I *do* need to go through the entire thing and use the same notation everywhere!
What a great video. I'm reading my way through the RISC-V documentation and the various projects around it, including QEMU for some days now. On my desk sits a MangoPi MQ-Pro, I have "the real thing" at my hands too. But I never understood the pure genius in the design of that architecture until seeing your excellent video. Thanks a lot! Perhaps, if you don't mind, there is one question left for me. I understood, there are no flags. But my mind refuses to get the hang on having no carry flag. I must admit, I went through processors like Z80, 8080, 80x86,68k and 6502 but no real RISC one until now. So...could you explain why there seems to be nothing like "shift left through carry"? Isn't such a thing needed? 🤔
This is discussed in section 2.4 of: The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, Document Version 20191213. You can get yours from here: riscv.org/technical/specifications/ I am not following your point of mentioning "shift left through carry" in this context other than to use it as a way to get the carry flag into an accumulator for a subsequent branch?
@@JohnsBasement thanks for pointing out the location of that in the specs, I'll read that part again. I've read through some of my old Z80 sources and you're right. Most of the time, Carry-Flag is used for realizing loops or for checking results of e.g. I/O after shifting/rotating it by an amount of bits. Everything of that could be done with direct comparisions to zero/nonzero or and and/or, followed by such a conditional branch. So it seems, that is purely habit on my side.
Flags in general are needed when you have separate compare and conditional branch instructions, to keep enough state from the compare (or other arithmetic) to make a decision. The carry flag in particular is needed for unsigned comparisons, while the V flag is needed for signed comparisons. RISC-V compares two registers and branches (or not) in one instruction, so no intermediate storage is needed. Both signed and unsigned conditional branches are provided. So that's the major use of flags in general simply not needed. On 8 bit and to a lesser extent 16 bit CPUs you are very often dealing with program variables that are larger than the registers/ALUs and the carry flag is needed to efficiently implement multi-precision adds and subtracts. When you have a 32 bit or especially 64 bit CPU it becomes very rare to need multi-precision arithmetic. The third use for a carry flag is detecting overflow. The RISC-V ISA manual covers that topic.
Hi John, thanks so much for the work you've done in getting people started in RV. I'm an EE student at ODU and am looking for some more hands on examples for the beginner-intermediate assembly programmer... since you're experienced in this space I was hoping you might be able to recommend some links to help in working with interrupts/WDTs, sensors in particular? Thanks again, great work here.
A serious and thorough reading of the privileged spec is what you want to do here. Spending some time tinkering with QEMU should help too. We're starting to see cheap RISC-V processors come out on eval boards these days. I'd expect that we will start seeing some projects getting posted on sites like Spartkun and Adafruit any time now. I have some messy notes on tinkering with this stuff on QEMU that I hope to put into a github project and maybe record some TH-cam videos to discuss them. Only so many hours in a day. :-/
@@JohnsBasement Thanks for the reply! I do realize this is a relatively new ISA (albeit with a long history), but for someone who isn't a CS major, and maybe for others at this point in their RV knowledge, the hands on with sensors especially would help as a catapult into more difficult topics!
@@kevinclaypool6345 If you have not yet noticed, Sean Hymel is doing a TH-cam series on interfacing sensors with an RV core on an FPGA that looks promising! Here is one that jumps in where you might see something interesting: th-cam.com/video/DtAwbKqLA5Y/w-d-xo.html
@@JohnsBasement Yes, exactly. And these hidden instructions such as trap instruction from privileged, is not allow user to use for program typically. It’s for computer to handle computing error.
@@JohnsBasement more specifically, this list doesn’t also contain CSR instructions, Environment instructions such as call and break, and synch instructions of RV32I.
@@aeebeecee3737 I updated the doc since I recorded this. Priv insns are subject of new lectures I'm still working on. It appears that the fence insns were moved out of the base ISA.
I am so fortunate to have stumbled across your online resources. I will become a better engineer due to the content that you have produced. Thank you so much!
I'm glad to know I could help!
I just finished the game "Turing Complete" which makes you build a simple computer with 8 bit registers and 32 bit instructions. It's amazing to see similarities between the game's proposed computer architecture and RISC-V. Thank you for the overview.
You're very welcome! Glad it was useful.
The same for me
Thank you very much! Now that ESP-C3 is out, knowledge of RISC-V gets more practical.
I believe that there is going to be a big future for RISC-V in both small and big systems!
Just stumbled on this. I haven't worked on hardware for... well.. let's just say I'm not as pretty now as i was back then, but I was able to follow along the entire lecture! Hurray my brain still works! Thanks and I will be looking over your book and your other videos because I'd like to learn more about RISC-V.
Thanks! I hope you have fun. The 'book' remains a work in progress. Constructive criticism is welcome.
First channel I ever subscribed after seeing just one video, beautiful and simple exposition
Thank you for such a kind review! Hopefully there'll be more RISC-V stuff this year.
I was able to use the RISC V documentation to get the same information, but you make it much easier and are very to the point with the big picture.
Thanks!
This video is absolutely amazing! So clear and to the point, thanks John!
Thanks for such kind words! You are welcome.
This was an excellent resource for my RISC-V implementation. I just did the integer base and may try a few extensions next.
Thanks. I think RISC-V has great potential.
Your lectures and your book are a gift, you're helping me so much. Thank you.
Happy Holidays!
@@JohnsBasement Happy holidays! :)
I just found your channel, keep up the good work, fantastic.
Thank you SO much. Your explanation is so clear with depth.
You're very welcome!
Thank you for the video and the documents. So very helpful: I feel a little cleverer now.
Glad I could help
Legend! Thank you very much
That’s actually such great video!!
Thanks. I'm glad SOMEBODY liked it!
Please forgive my confusion. When I heard RISC was doing a Vector chip I assumed that would mean it would have onboard vector graphics libraries for accelerating and simplifying processes similar to Flash, Inkscape, or Processing.js. I would expect a collection of built in libraries of various vector fonts onboard. I was looking forward to being able to make a few simple calls in Assembly and open a window of colorful vector based elipses, arcs, gradients, animated vector text, etc..
When I was an animation student at DeAnza I encouraged a small startup called Macromedia to develop vector animation tools. The idea being one could transmit full screen animations using tiny amounts of data back when 28.8K modems were the norm and bandwidth was dismal. Today microprocessors are the norm. I was picturing handheld devices that can communicate with one another using said scalable graphics and data. We have come full circle where now once again small data is valuable for transmitting between tiny devices.
I could go on and on about all the wondrous things one could do.
Is that not what this chip is about at all? I am completely baffled! ???
@@dillingerlee2536 The V in RISC-V means 5 in this context... As in version 5. And 'vector' instructions in the context of RISC-V (at the moment) refer to vector registers (a one dimensional array.)
@@JohnsBasement Ah I see! But there is a Vector chip on the near horizon right? I heard folks were already working on an OS for it. If so there should be an emulator for qemu in the near future, yes? Or have I completely got my wires crossed on the topic?
You are awesome!
@@Gaafet 😂... Why thank you!
Nicely explained with comparison with other ARCHS
Thanks for saying so!
Great explanation….I got a great overview of RISC V
Thank you for saying so!
Finally, I've been looking for a simple explanation of risc-v for a long time and this is just what I needed.
I'm about to make a RV32I compliant processor in minecraft, so you could use gcc to program it instead of the usual machine code.
And if I'm really feeling autistic i could make it RV32G and run fucking linux in minecraft. Very unlikely...
Ya know, it just might turn out that it comes together.
yep x86 implementations ive worked with have all had a similar convention about the always zero bit, it was even in the same place iirc
great explanation
in your latest edition of RISC-V assembly language programing(Draft v0.18.3-0-g8a08bae), in 83rd page where you have combined both description and instruction format of instructions. In the jalr instruction operation description, you have used ^ operator instead of & operator but in 81 page you have given & operator in description. so change ^ operator to &
Ugh.... that is actually correct. the big wedge is a logical AND. I can see that I was, however, inconsistent by using the & on a prior page. I *do* need to go through the entire thing and use the same notation everywhere!
Thanks John, So great video!
Thanks! I'm glad it helped.
Very good lecture and pdf for us to learn
Thanks and welcome
What a great video. I'm reading my way through the RISC-V documentation and the various projects around it, including QEMU for some days now. On my desk sits a MangoPi MQ-Pro, I have "the real thing" at my hands too. But I never understood the pure genius in the design of that architecture until seeing your excellent video. Thanks a lot!
Perhaps, if you don't mind, there is one question left for me. I understood, there are no flags. But my mind refuses to get the hang on having no carry flag. I must admit, I went through processors like Z80, 8080, 80x86,68k and 6502 but no real RISC one until now. So...could you explain why there seems to be nothing like "shift left through carry"? Isn't such a thing needed? 🤔
This is discussed in section 2.4 of: The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, Document Version 20191213. You can get yours from here: riscv.org/technical/specifications/
I am not following your point of mentioning "shift left through carry" in this context other than to use it as a way to get the carry flag into an accumulator for a subsequent branch?
@@JohnsBasement thanks for pointing out the location of that in the specs, I'll read that part again. I've read through some of my old Z80 sources and you're right. Most of the time, Carry-Flag is used for realizing loops or for checking results of e.g. I/O after shifting/rotating it by an amount of bits. Everything of that could be done with direct comparisions to zero/nonzero or and and/or, followed by such a conditional branch. So it seems, that is purely habit on my side.
Flags in general are needed when you have separate compare and conditional branch instructions, to keep enough state from the compare (or other arithmetic) to make a decision. The carry flag in particular is needed for unsigned comparisons, while the V flag is needed for signed comparisons. RISC-V compares two registers and branches (or not) in one instruction, so no intermediate storage is needed. Both signed and unsigned conditional branches are provided. So that's the major use of flags in general simply not needed. On 8 bit and to a lesser extent 16 bit CPUs you are very often dealing with program variables that are larger than the registers/ALUs and the carry flag is needed to efficiently implement multi-precision adds and subtracts. When you have a 32 bit or especially 64 bit CPU it becomes very rare to need multi-precision arithmetic. The third use for a carry flag is detecting overflow. The RISC-V ISA manual covers that topic.
It would be super interesting to make a 32 bit core, but tape it out on silicon carbide so it could be run at 25 GHz rather than 2.5 GHz.
Indeed it would!
Hi John, thanks so much for the work you've done in getting people started in RV. I'm an EE student at ODU and am looking for some more hands on examples for the beginner-intermediate assembly programmer... since you're experienced in this space I was hoping you might be able to recommend some links to help in working with interrupts/WDTs, sensors in particular? Thanks again, great work here.
A serious and thorough reading of the privileged spec is what you want to do here. Spending some time tinkering with QEMU should help too. We're starting to see cheap RISC-V processors come out on eval boards these days. I'd expect that we will start seeing some projects getting posted on sites like Spartkun and Adafruit any time now.
I have some messy notes on tinkering with this stuff on QEMU that I hope to put into a github project and maybe record some TH-cam videos to discuss them. Only so many hours in a day. :-/
@@JohnsBasement Thanks for the reply! I do realize this is a relatively new ISA (albeit with a long history), but for someone who isn't a CS major, and maybe for others at this point in their RV knowledge, the hands on with sensors especially would help as a catapult into more difficult topics!
@@kevinclaypool6345 If you have not yet noticed, Sean Hymel is doing a TH-cam series on interfacing sensors with an RV core on an FPGA that looks promising! Here is one that jumps in where you might see something interesting:
th-cam.com/video/DtAwbKqLA5Y/w-d-xo.html
this is a really helpful video thank you
Glad it was helpful!
overall good content to learn riscv
@@aloysious8482 thanks!
thank you.
🙏
RIP x86!!...Thanks
The ground is starting to shake!
Thanks
No problem
excellent. thank you
Thank you very much!
Sir it's really incredible video ..+ how can get that PDF?
Thanks!
There is a link in the description below the video.
Bravo
Thank you.
thanks for your video. Where I can get this pdf?
See links in the description below the video.
what is the name of the book which you are reading from ?
It is a bunch of personal notes I have cobbled together over the years that might be of interest to others. Links are in the video description.
These are not the all instructions of RV32I. These are appearance instructions for users. RV32I has hidden instructions for computer.
Which ones are you referring to? You mean the privileged instructions? Fence?
@@JohnsBasement Yes, exactly. And these hidden instructions such as trap instruction from privileged, is not allow user to use for program typically. It’s for computer to handle computing error.
@@JohnsBasement more specifically, this list doesn’t also contain CSR instructions, Environment instructions such as call and break, and synch instructions of RV32I.
@@aeebeecee3737 I updated the doc since I recorded this. Priv insns are subject of new lectures I'm still working on. It appears that the fence insns were moved out of the base ISA.
@@JohnsBasement that’s cool, and thanks a lot for your replying about my comment.