It's funny, I designed my own ideal, highly compact instruction set with just basic undergraduate CS knowledge decades ago and risc V is surprisingly similar - but I have to say not as good in many ways. You only need 4 (long as you like) registers per core with 2 main ones that all core operations use as parameters. Destination can be set to any core register... Many simpler cores that can share half (or more, sometimes even less) the number of scalar/vector-switchable execution units. Each core also has a data type, value size and vector length register... I'd like to see research into a recursive 4 core design as 4 cores are the maximum that can directly connect to each other without I/O lines crossing (in 2D) - so 4 core groups grouped into 4, 4 of those, etc... Now-a-days main memory should be integrated too (in most cases).
That sound really interesting, that could be nice if you got in touch with the people working on the draft on github.com/riscv/riscv-v-spec/ Im not part of the project (yet) but I m desperate for the V extension to happen :D
![ละลาย (LALALYE) - DAOU PITTAYA ต้าห์อู๋ พิทยา [OFFICIAL MV]](http://i.ytimg.com/vi/wo6r9TgausI/mqdefault.jpg)
Isn't this the same guy that that co-designed the X86 AVX512 instruction set at Intel?
I think that's what he said in a previous video.
It's funny, I designed my own ideal, highly compact instruction set with just basic undergraduate CS knowledge decades ago and risc V is surprisingly similar - but I have to say not as good in many ways. You only need 4 (long as you like) registers per core with 2 main ones that all core operations use as parameters. Destination can be set to any core register... Many simpler cores that can share half (or more, sometimes even less) the number of scalar/vector-switchable execution units. Each core also has a data type, value size and vector length register... I'd like to see research into a recursive 4 core design as 4 cores are the maximum that can directly connect to each other without I/O lines crossing (in 2D) - so 4 core groups grouped into 4, 4 of those, etc... Now-a-days main memory should be integrated too (in most cases).
Sounds interesting! I'd like to chat to you about this someday. :-)
That sound really interesting, that could be nice if you got in touch with the people working on the draft on github.com/riscv/riscv-v-spec/
Im not part of the project (yet) but I m desperate for the V extension to happen :D
looks much like a Cray-1