"BAG: A Process-Portable Framework for Generator-based AMS Circuit Design"- Eric Chang

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  • เผยแพร่เมื่อ 18 ธ.ค. 2019
  • Abstract:
    As the nature of scaling has shifted due to both technological and economic barriers, innovations in systems and circuits have become increasingly necessary to meet the needs to next generation designs. However, the stringent and unintuitive design rules and increased interconnect resistance/capacitance in process nodes under 10nm has severely lengthen the time spent in post-layout verification and limit designers' ability to explore new circuit designs. To significantly improve designers' productivity, we advocate for a generator-based design approach, where instead of designing one circuit instance, the designer captures their methodology as an executable circuit generator that consists of parameterized procedures which can produce schematic, layout, behavioral model, and verification test benches from input specifications. With these generators, designers can incorporate fully automated design iteration loops on accurate post-layout simulation data in their design procedure. More importantly, such generators can easily produce many circuit instances for similar applications with different specifications, which promotes design reuse and simplifies complex system design. This talk presents an overview of BAG, a Python framework that enables the development of process-portable circuit generators. This talk will also feature a live demo showcasing the typical generator-based design flow, with an emphasis on the challenges of process-portable layout generator development.
    Biography: Eric Y. Chang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley in 2011. From 2011 to 2014, he was a full-time Researcher at Oracle Labs, where he worked on silicon photonics under the DARPA POEM program. Afterwards, He worked on design automation of analog and mixed-signal circuits at University of California, Berkeley, and will graduate with a Ph.D. degree in 2019. He is currently the CTO of Blue Cheetah Analog Design Inc., a startup specialized in development of automated analog mixed-signal IP generators.

ความคิดเห็น • 4

  • @ldmoriarty
    @ldmoriarty 4 ปีที่แล้ว +2

    Can't wait to try it !!
    awful echo in the demo but worth tolerating.

  • @user-zu2nk7zx2b
    @user-zu2nk7zx2b 4 ปีที่แล้ว

    nice to see this, especially in mixed signals design area.

  • @zhengxionghou5433
    @zhengxionghou5433 2 ปีที่แล้ว

    a good tool to accelerate AMS design

  • @cantkeepitin
    @cantkeepitin ปีที่แล้ว

    I believe the analog designers are very reluctant to this because nobody sees any problem in making a schematic, this is the fun part, why should a tool do it?