ES3-3- "ADC-based Wireline Transceivers" - Yohan Frans
ฝัง
- เผยแพร่เมื่อ 17 ธ.ค. 2019
- Abstract:
The emergence of PAM4 electrical signaling standard at 56Gb/s and 112Gb/s has caused wider adoption of ADC-based transceiver. In this talk, we will start with a high level overview of ADC-based transceiver and its power/performance comparison to the analog/mixed-signal transceiver. We will then discuss more detailed aspects of ADC-based transceiver design such as adaptive hybrid equalization in analog and digital domain, RX Front-end design, ADC requirement and design considerations, and clocking architecture.
Biography: Yohan Frans received B.S. degree in electrical engineering from Bandung Institute of Technology, Indonesia in 1995 and M.S. degree in electrical engineering from Stanford University, California in 2001.
From 2001 to 2012, he was with Rambus Inc. where he worked on high-performance and low-power serial links and memory interfaces as circuit design engineer, circuit architect, and design manager. Since 2012 he has been with Xilinx Inc, San Jose, CA. He is currently leading design teams as Senior Engineering Director in Xilinx Serdes Technology Group, developing high-speed wireline transceivers for advanced FPGA.
His current interests include high-speed mixed-signal circuit design, serial link architecture, transmitter/receiver design, PLL/DLL, memory interfaces, and low-power circuit architectures. He is a member of ISSCC Wireline Sub-committee.
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great
Amazing talk. Thank you! Would it be possible to get more information about inverter-based ctle?
where are you getting the clock for sample and hold circuit or ADC ?
input of DFE is o/p of ADC which is digital, wonder how dfe can equalize a saturated signal.
Didn't know that industry made PAM4 a standard for 56gbps
how do you calculate cross talk and why is it very nonlinear with frequency ?
wow