USER DEFINED PRIMITIVES

[@anuragagarwal4576]

Since this is a sequential portion at 27:04, why we are not taking "output reg [5:0] count" instead of "output [5:0] count" ?

[@VivekVerma-oo3dx]

we require reg for holding the prev state that can be used for next state but here in ripple counter though it is a sequential circuit but we have completed the sequential part by t flip flop and need not to hold the count state thats why we didn't used reg with count here

[@phaneendrakumar658]

Here I think we cannot instantiate any modules/UDP inside a UDP. But how did you instantiate TFF UDP inside the ripple_counter UDP at 26:32
( which is a UDP)??

[@Deepak-ip1se]

For T fip flop shouldn't we take T as one of the inputs?

[@abhijeetchauhan4111]

not able to instantiate the udp files in Vivado. Do we have to save those files with different extensions ?

[@prajwal4245]

Ripple counter should be a module r8????

[@shambhabchaki5408]

You have clearly said no vector output is possible while using primitive, only one bit output is permitted. But switch to 27'12'', you have clearly used 'count' vector as output. Why?

[@avisekhghosh2757]

because count is a vector ......but count[anyvalue] is just a single bit.
by no vector output he meant that you cannot simply have multiple outputs either consisting of various variables or a vector.

[@knowledgeunlimited]

@@avisekhghosh2757 he told declaration of vector itself is not possible in udp right? correct me if i'm wrong.

[@anuragagarwal4576]

@@avisekhghosh2757 Since this is a sequential portion at 27:04, why we are not taking "output reg [5:0] count" instead of "output [5:0] count" ?

[@avisekhghosh2757]

@@anuragagarwal4576 you only use 'reg' when you are assigning that variable inside an always block.
In your example there is no alwaya block. The primitive module only consists of submodules, hence wire will do the job.
Using 'reg' has nothing to do with sequential circuit. Its just a rule that the assigned values inside an always block should be a reg type. Its depends on the synthesizer and your logic, whether this reg type get synthesized into a series of actual flip flops or just a wire bus.

[@anuragagarwal4576]

@@avisekhghosh2757 Ok, so here, since we are using all Flip Flops concurrently, we donot actually need to store them, they will run continuously and hence there is no need for a "reg" type. Correct ?

[@vandan5036]

hey in level-sensitive d type latch over output is next state(q_new) and it must be a reg type but in the above code present state (q) is declared as reg
we have to declare *output reg q_new*

[@madhursharma4445]

😁

[@subhrasen1395]

there is no separate variable q_new..it is just a comment...both prev state and next states are stored in variable q only

[@mrpossible5696]

6:41