VERILOG DESCRIPTION STYLES

[@yaserc.3363]

Thank you, correct me if I'm wrong I think in 19:23 this is a Demux not a decoder since we have a selector

[@Elnino12336]

when input is only 1 in decoder it will become de mux

[@vandan5036]

in NAND LATCH it is active low and s is at top and in its front there is q and in front of R there should be q_bar

[@arghya.7098]

yes, you're right

[@shirsenduacharyya9443]

the decoder code is showing error and non synthesizable- ERROR - sel is not a constant
module Simple_decoder_1_to_4(in,sel,out);
input in;
input [0:1]sel;
output [0:3] out;
assign out[sel]=in; // when LHS is variable we get a decoder
endmodule

[@arghya.7098]

you used 3 variables but declared 2 variables. that might cause an error

[@ghost_riderrr]

@@arghya.7098 he declared all the variables ig

[@murugeshwarana2427]

"assign" statement is always active, that is, whenever the values of RHS operands changes, the new value of LHS is evaluated and updated on the net.
But in the code explain by the professor, the LHS has a variable on the LHS which is illegal according to the above definition of assign statement.
Thus, the code can be modified as below
module generate_decoder (out,in,sel);
input in;
input [1:0]sel;
output reg [3:0]out;
always@(in,sel)
begin
out[sel] = in;
end
endmodule
In the above code, "out[sel] = in;" is synthesized as decoder as explained the professor.

[@RAN-DOM___46777]

@@murugeshwarana2427 Thank you. Your ans really helped.

[@nenavathharisingh3231]

Isn't that decoder a dmux ??

[@arghya.7098]

i guess he mistakenly told demux and decoder as same thing

[@UTube4075]

Best book for Verilog????

[@يعقوبالبدر-ز9ز]

guys,does anyone know ho to get the slides which prof explain?

[@mrkumar7181]

Why reg is not used ?

[@mrpossible5696]

Y

[@arghyaray9011]

Can anyone help on the following !!!
The decoder code is showing error and non synthesizable- ERROR - sel is not a constant
module Simple_decoder_1_to_4(in,sel,out);
input in;
input [0:1]sel;
output [0:3] out;
assign out[sel]=in; // when LHS is variable we get a decoder
endmodule

[@abhishekagrawal542]

but decoder ckt will not having selection line

[@arghya.7098]

you used 3 variables but declared 2 variables. that might cause an error

[@murugeshwarana2427]

"assign" statement is always active, that is, whenever the values of RHS operands changes, the new value of LHS is evaluated and updated on the net.
But in the code explain by the professor, the LHS has a variable on the LHS which is illegal according to the above definition of assign statement.
Thus, the code can be modified as below
module generate_decoder (out,in,sel);
input in;
input [1:0]sel;
output reg [3:0]out;
always@(in,sel)
begin
out[sel] = in;
end
endmodule
In the above code, "out[sel] = in;" is synthesized as decoder as explained the professor.