the decoder code is showing error and non synthesizable- ERROR - sel is not a constant module Simple_decoder_1_to_4(in,sel,out); input in; input [0:1]sel; output [0:3] out; assign out[sel]=in; // when LHS is variable we get a decoder endmodule
Can anyone help on the following !!! The decoder code is showing error and non synthesizable- ERROR - sel is not a constant module Simple_decoder_1_to_4(in,sel,out); input in; input [0:1]sel; output [0:3] out; assign out[sel]=in; // when LHS is variable we get a decoder endmodule
in NAND LATCH it is active low and s is at top and in its front there is q and in front of R there should be q_bar
yes, you're right
Isn't that decoder a dmux ??
i guess he mistakenly told demux and decoder as same thing
the decoder code is showing error and non synthesizable- ERROR - sel is not a constant
module Simple_decoder_1_to_4(in,sel,out);
input in;
input [0:1]sel;
output [0:3] out;
assign out[sel]=in; // when LHS is variable we get a decoder
endmodule
you used 3 variables but declared 2 variables. that might cause an error
Best book for Verilog????
Why reg is not used ?
Y
Can anyone help on the following !!!
The decoder code is showing error and non synthesizable- ERROR - sel is not a constant
module Simple_decoder_1_to_4(in,sel,out);
input in;
input [0:1]sel;
output [0:3] out;
assign out[sel]=in; // when LHS is variable we get a decoder
endmodule
but decoder ckt will not having selection line
you used 3 variables but declared 2 variables. that might cause an error