Ferrite on VCC / Power delivery pin really helps to increase impedance for the frequency where we wanted to increase attenuation by carefully selecting the ferrite bead based on the attenuation curve and frequency response, and decoupling cap near the PIN can work line a local energy source , could you please suggest more details to avoid ferrite on power delivery bus if this really creates a problem ?
Can you please explain 1. what is ground looping? & how to avoid it? 2. What is Analog ground & Digital ground ? & Why and How to handle it in same PCB ?
Hi Jainshankar, we'll tackle this in our upcoming Q&A video! For now, take a look at our earlier mixed signal videos if you want to learn more. th-cam.com/video/8iz57vDKdh4/w-d-xo.html th-cam.com/video/S6PNYKxJsdk/w-d-xo.html th-cam.com/video/YWDxLHfsx-U/w-d-xo.html
Thank you a lot for the explanation Mr. Zach, you really help me to understand better about differential pairs. Let me ask you a doubt about differential pair in USB design that I saw this week: Can I put pull down resistors in differential pairs?
For USB you would do this according to the USB stadnard. We have a blog on the Altium site where we show this, we also detailed this in another video: th-cam.com/video/4LwnEaNvG8I/w-d-xo.html In general you would not do this unless you need level shifting or unless the protocol is designed as an open drain differential protocol, which is something you might do with specialty logic. You would do something similar in some differential pair receiver designs as this is how the original receivers were built from discrete components, but today you would not need to do this because those receiver circuits (and their termination) is built into the IO stage on your IC. In something like an FPGA it would be selectable when you configure the device.
If I run two pairs of differential traces along the exact same path that reference the same plane, but are on opposite sides of the plane, will they couple differential or common mode noise to each other? Ex plane sig
May be i am missing something here. But, when you have d+ and d- , the magnetic lines of force between them add up as they are pointing upwards between the two traces. However if both the signals are having the same polarity, the magnetic lines of force cancel. Similarly, electric lines of forces for opposite polarity stay within the two traces, while, for two of the same polarity signals, the electric lines of force should be away from each other. So, in the example shown around 24 min, i am confused on the explanation. Please clarify.
With differential pairs, there is only constructive interference of electric and magnetic field between the two traces, but farther away from the two traces there is destructive interference. This is why differential pairs are preferable for sending serial data over a cable, for example; the fields are weaker away from the two conductors and the same occurs in a PCB. With common mode, the constructive interference happens outside the two traces rather than between them, which is why common mode currents are such a problem, especially on cables. It is the common mode currents that create large radiation that can cause an EMC failure, and this can occur despite the fact that the device can still function as intended.
Hi Zach, after having carefully routed a usb differential pair with separation, line width, and length tune, how could we possibly verify that it is working at the impedance we meant to design? Any equipment to use and how is the setup?
If you are trying to measure the impedance directly you would use a vector network analyzer (VNA). This requires replicating the designed traces onto a test coupon. VNAs are expensive instruments, so what most people will do is use a TDR measurement as it is a less expensive instrument. If you have asked your manufacturer to do impedance testing, they will most likely do this with a TDR measurement.
There are a few ways to do this. The best way depends on the rise time of the signal being transmitted on a differential pair. The signals on each side of the differential pair need to be rising at the same time, so the maximum mismatch is basically equal to the rise time. To be safe, set a low safety limit on this, something like under 50% as this will provide a big allowance for random skew, jitter, and ISI. So for example, if the Rise time is 100 ps, and you set a 20% limit for safety, your mismatch would be 20 ps and the link could tolerate no more than 80 ps of jitter. You would then take that 20 ps and convert it to a length using the propagation delay, which is easy to calculate or you can use the impedance calculator to get the propagation delay.
Thanks for this Zach. I just started to understand differential pair, recently I encountered a situation where I have to cross usb differential data due to the way the USB micro-B D+ and D- are constructed it is not in correspondence with the Source D+ D- coming from the controller. I don't know if it is fine to cross D+ D- with each other, I know there will be need to use via, and How? Also, I am using 4 layers stack up, sig gnd gnd sig, should the via go from layer 1 to 4 of just from layer 1 to 2, where those differential data will reference.
That's a good question. Probably the easiest method is to switch the USB connector to the other layer. If you flip it over you can then route directly into the connector pins, and you can just place the via transition at the connector pins or at the chip pins, either way should work fine. You also can route those pairs on the back layer, just cross the pairs over by the output of your USB host controller and add a length tune section to make up any length difference. If instead you are designing to the 3.0 (SuperSpeed) standard, you can swap the SSRX and SSTX pairs. This is because the SuperSpeed capable transceiver will send data sequences when instantiating the link to determine if any lane polarity inversion is present. Unfortunately this type of inversion is not implemented in USB 2.0 with the D+/D- pair. I would recommend moving to USB-C because that is the direction everything is going anyways.
Hi MrAlistar28, we just filmed a video in response to explain this, so stay tuned for that one in the next few weeks. The short answer to your question is: I find that the inhomogeneity tends to arise near the driver, and the idea is to resynchronize the signals so that anywhere else noise is received on the interconnects, it can be eliminated by the receiver because the rest of length of those traces is in phase. But if you generalize the recommendation to other situations, like if you need to make a lot of bends to complete a route, then you could put some small sections very close to where those length mismatches occur.
When I do length matching, it often can't tightly couple with the other differentially routed trace since it moves away from the other trace. To what degree does this matter?
Hi dmxspider, So you've brought up two points here: One is about keeping the traces close together, and the other is about keeping them the same length. You're basically trying to balance noise suppression and prevent mode conversion. If you've kept everything the same length, then you will very easily suppress mode conversion as long as there is no additional asymmetry (impedance variations from parasitics, roughness variations, etc.) along the length of the route. If you keep everything tightly coupled together and the same length, you will have also minimized noise emitted from the signal travelling on the differential pair. This is very important for high speed signals with fast edge rates, which can have strong emission due to their high dI/dt switching at the driver and high dV/dt switching along the transmission line. The ability for the opposite polarity signals to emit lower noise than a single-ended signal is one of the big advantages of differential pairs. If you start to have some separation between the traces, then you have less noise suppression and a little bit of mode conversion to differential mode, but only in that region where there is some separation. If it's a small area I wouldn't worry about it, but if you see during testing or simulation that it creates excess loss then you should try to avoide creating asymmetry.
When you don't have the optiond to place the aggressor line far from the differencial pair, if we place vias between aggressor and first differencial pair line and also vias on the other side near the second differencial pair line with the same distance (so the change in capacitance be the same for both lines) could that be a solution to shield the pair? Thank you.
You have to be careful with this strategy. Placing a line of vias between two traces is something that is supposed to be used in RF design, but somehow it got adapted over to digital design and now everyone does it when they shouldn't. Grounded vias or a region of copper pour with a row of vias is supposed to suppress propagation of radiation up to specific frequencies, they are designed such that the lowest order resonance in the cavity defined by the two vias is at much higher frequency than the specific frequency you want to shield against, which will then be effective for all lower frequencies. The problem with digital is that you might excite the resonances in the structure anyways because digital signals have content up to infinite frequency, so you might create a new problem if the via spacing is too large. For digital, the better solution is to widen the traces a little bit, use a thinner dielectric, or both. Also bigger spacing is important. You can usually solve crosstalk or EMI problems by adjusting the PCB layout or the stackup, and if you do that you might find that the use of copper pour and via fences vias isn't always needed.
Regarding the ferrite beads placed in series with vcc, i sometimes when dealing with sensors like PIR i place a ferrite beads before the input vcc of the pir with bypass cap and also after the output pin of the pir to filter high frequency noise. ( I just put it before the sensor) do that also could cause problems?
Hi Fedi, thanks for watching! Regarding the ferrite, I was referring specifically to the case of placing a ferrite bead on a PDN that supplies power to a large high speed processor like an FPGA. This component could draw large bursts of current into the PDN, and the impedance of the ferrite creates larger voltage fluctuations in mid-range frequencies (around 100 MHz to 1 GHz), which can then produce noise on the IOs from that component. The better option to remove this noise with capacitors. For DC regulators (like an LDO) and load components that only draw DC power, it's not really a problem because you are not drawing broadband current pulses into the PDN, so you don't need to worry about the impedance at mid-range frequencies. There is an app note from Analog Devices that nicely shows measurements where a ferrite did provide noise reduction in the case where a DC voltage is supplied to a static impedance (only drawing DC current). Still, the standard way to make that regulator is to provide low-pass filtering with capacitors to GND, so you might not always need the ferrite. For a PIR sensor, I would assume it is only responding to slow movements that are closer to DC, but you likely have an op-amp that produces the output and probably has to respond quickly to those changes in input, so you might excite some transient. If you've gotten it to work accurately and you've tested it then I won't tell you to not use ferrites, but those are things to think about when using inductive components as they might create a challenge with measurement.
It is a common practice and practical to use single voltage source for multiple loads or components (FPGA, MCU, buffers, etc.) to save on cost. The ferrite bead is effective at reducing the coupling of noise from other switching loads in the same voltage rail. The capacitor is placed right after the ferrite bead to reduce or counter the impedance introduced by the ferrite bead. However, this setup sometimes causes a small amount of oscillations across the capacitor if the values are not properly selected. Sometimes, it is better to use a small value of resistor instead of ferrite bead.
Ferrite on VCC / Power delivery pin really helps to increase impedance for the frequency where we wanted to increase attenuation by carefully selecting the ferrite bead based on the attenuation curve and frequency response, and decoupling cap near the PIN can work line a local energy source , could you please suggest more details to avoid ferrite on power delivery bus if this really creates a problem ?
Many thanks for the good explanation!
Can you please explain
1. what is ground looping? & how to avoid it?
2. What is Analog ground & Digital ground ? & Why and How to handle it in same PCB ?
Hi Jainshankar, we'll tackle this in our upcoming Q&A video! For now, take a look at our earlier mixed signal videos if you want to learn more.
th-cam.com/video/8iz57vDKdh4/w-d-xo.html
th-cam.com/video/S6PNYKxJsdk/w-d-xo.html
th-cam.com/video/YWDxLHfsx-U/w-d-xo.html
@@Zachariah-Peterson Thank you
Thank you a lot for the explanation Mr. Zach, you really help me to understand better about differential pairs. Let me ask you a doubt about differential pair in USB design that I saw this week: Can I put pull down resistors in differential pairs?
For USB you would do this according to the USB stadnard. We have a blog on the Altium site where we show this, we also detailed this in another video: th-cam.com/video/4LwnEaNvG8I/w-d-xo.html
In general you would not do this unless you need level shifting or unless the protocol is designed as an open drain differential protocol, which is something you might do with specialty logic. You would do something similar in some differential pair receiver designs as this is how the original receivers were built from discrete components, but today you would not need to do this because those receiver circuits (and their termination) is built into the IO stage on your IC. In something like an FPGA it would be selectable when you configure the device.
Thanks a lot ❤
19;21 rather than moving aggressive trace can't we place guard trace. To avoid interference
If I run two pairs of differential traces along the exact same path that reference the same plane, but are on opposite sides of the plane, will they couple differential or common mode noise to each other?
Ex
plane
sig
The planes do provide high shielding for these differential pairs.
May be i am missing something here. But, when you have d+ and d- , the magnetic lines of force between them add up as they are pointing upwards between the two traces. However if both the signals are having the same polarity, the magnetic lines of force cancel. Similarly, electric lines of forces for opposite polarity stay within the two traces, while, for two of the same polarity signals, the electric lines of force should be away from each other. So, in the example shown around 24 min, i am confused on the explanation. Please clarify.
With differential pairs, there is only constructive interference of electric and magnetic field between the two traces, but farther away from the two traces there is destructive interference. This is why differential pairs are preferable for sending serial data over a cable, for example; the fields are weaker away from the two conductors and the same occurs in a PCB. With common mode, the constructive interference happens outside the two traces rather than between them, which is why common mode currents are such a problem, especially on cables. It is the common mode currents that create large radiation that can cause an EMC failure, and this can occur despite the fact that the device can still function as intended.
Hi Zach, after having carefully routed a usb differential pair with separation, line width, and length tune, how could we possibly verify that it is working at the impedance we meant to design? Any equipment to use and how is the setup?
If you are trying to measure the impedance directly you would use a vector network analyzer (VNA). This requires replicating the designed traces onto a test coupon. VNAs are expensive instruments, so what most people will do is use a TDR measurement as it is a less expensive instrument. If you have asked your manufacturer to do impedance testing, they will most likely do this with a TDR measurement.
How to calculate the mismatch allowed b/w lines of diff pair
There are a few ways to do this. The best way depends on the rise time of the signal being transmitted on a differential pair. The signals on each side of the differential pair need to be rising at the same time, so the maximum mismatch is basically equal to the rise time. To be safe, set a low safety limit on this, something like under 50% as this will provide a big allowance for random skew, jitter, and ISI. So for example, if the Rise time is 100 ps, and you set a 20% limit for safety, your mismatch would be 20 ps and the link could tolerate no more than 80 ps of jitter. You would then take that 20 ps and convert it to a length using the propagation delay, which is easy to calculate or you can use the impedance calculator to get the propagation delay.
Awesome video!
Glad you enjoyed it
Thanks for this Zach.
I just started to understand differential pair, recently I encountered a situation where I have to cross usb differential data due to the way the USB micro-B D+ and D- are constructed it is not in correspondence with the Source D+ D- coming from the controller.
I don't know if it is fine to cross D+ D- with each other, I know there will be need to use via, and How?
Also, I am using 4 layers stack up, sig gnd gnd sig, should the via go from layer 1 to 4 of just from layer 1 to 2, where those differential data will reference.
That's a good question. Probably the easiest method is to switch the USB connector to the other layer. If you flip it over you can then route directly into the connector pins, and you can just place the via transition at the connector pins or at the chip pins, either way should work fine. You also can route those pairs on the back layer, just cross the pairs over by the output of your USB host controller and add a length tune section to make up any length difference.
If instead you are designing to the 3.0 (SuperSpeed) standard, you can swap the SSRX and SSTX pairs. This is because the SuperSpeed capable transceiver will send data sequences when instantiating the link to determine if any lane polarity inversion is present. Unfortunately this type of inversion is not implemented in USB 2.0 with the D+/D- pair. I would recommend moving to USB-C because that is the direction everything is going anyways.
@@Zachariah-Peterson thanks for this. I am working on that, but still finding it hard to get along with the USB C.
why do you say to apply length matching at the driver side? ive heard best to apply at transition points (right before a via). could you talk on this?
Hi MrAlistar28, we just filmed a video in response to explain this, so stay tuned for that one in the next few weeks. The short answer to your question is: I find that the inhomogeneity tends to arise near the driver, and the idea is to resynchronize the signals so that anywhere else noise is received on the interconnects, it can be eliminated by the receiver because the rest of length of those traces is in phase. But if you generalize the recommendation to other situations, like if you need to make a lot of bends to complete a route, then you could put some small sections very close to where those length mismatches occur.
Did I miss the "3W" and "5W" rule of thumb discussions ?
I'm not a fan of rules of thumb just because they tend to be overly conservative.
@@Zachariah-Peterson th-cam.com/video/D0X76Kbf8fQ/w-d-xo.html
When I do length matching, it often can't tightly couple with the other differentially routed trace since it moves away from the other trace. To what degree does this matter?
Hi dmxspider,
So you've brought up two points here: One is about keeping the traces close together, and the other is about keeping them the same length. You're basically trying to balance noise suppression and prevent mode conversion.
If you've kept everything the same length, then you will very easily suppress mode conversion as long as there is no additional asymmetry (impedance variations from parasitics, roughness variations, etc.) along the length of the route.
If you keep everything tightly coupled together and the same length, you will have also minimized noise emitted from the signal travelling on the differential pair. This is very important for high speed signals with fast edge rates, which can have strong emission due to their high dI/dt switching at the driver and high dV/dt switching along the transmission line. The ability for the opposite polarity signals to emit lower noise than a single-ended signal is one of the big advantages of differential pairs.
If you start to have some separation between the traces, then you have less noise suppression and a little bit of mode conversion to differential mode, but only in that region where there is some separation. If it's a small area I wouldn't worry about it, but if you see during testing or simulation that it creates excess loss then you should try to avoide creating asymmetry.
Thank you!
When you don't have the optiond to place the aggressor line far from the differencial pair, if we place vias between aggressor and first differencial pair line and also vias on the other side near the second differencial pair line with the same distance (so the change in capacitance be the same for both lines) could that be a solution to shield the pair? Thank you.
You have to be careful with this strategy. Placing a line of vias between two traces is something that is supposed to be used in RF design, but somehow it got adapted over to digital design and now everyone does it when they shouldn't. Grounded vias or a region of copper pour with a row of vias is supposed to suppress propagation of radiation up to specific frequencies, they are designed such that the lowest order resonance in the cavity defined by the two vias is at much higher frequency than the specific frequency you want to shield against, which will then be effective for all lower frequencies. The problem with digital is that you might excite the resonances in the structure anyways because digital signals have content up to infinite frequency, so you might create a new problem if the via spacing is too large.
For digital, the better solution is to widen the traces a little bit, use a thinner dielectric, or both. Also bigger spacing is important. You can usually solve crosstalk or EMI problems by adjusting the PCB layout or the stackup, and if you do that you might find that the use of copper pour and via fences vias isn't always needed.
Regarding the ferrite beads placed in series with vcc, i sometimes when dealing with sensors like PIR i place a ferrite beads before the input vcc of the pir with bypass cap and also after the output pin of the pir to filter high frequency noise. ( I just put it before the sensor) do that also could cause problems?
Hi Fedi, thanks for watching! Regarding the ferrite, I was referring specifically to the case of placing a ferrite bead on a PDN that supplies power to a large high speed processor like an FPGA. This component could draw large bursts of current into the PDN, and the impedance of the ferrite creates larger voltage fluctuations in mid-range frequencies (around 100 MHz to 1 GHz), which can then produce noise on the IOs from that component. The better option to remove this noise with capacitors.
For DC regulators (like an LDO) and load components that only draw DC power, it's not really a problem because you are not drawing broadband current pulses into the PDN, so you don't need to worry about the impedance at mid-range frequencies. There is an app note from Analog Devices that nicely shows measurements where a ferrite did provide noise reduction in the case where a DC voltage is supplied to a static impedance (only drawing DC current). Still, the standard way to make that regulator is to provide low-pass filtering with capacitors to GND, so you might not always need the ferrite.
For a PIR sensor, I would assume it is only responding to slow movements that are closer to DC, but you likely have an op-amp that produces the output and probably has to respond quickly to those changes in input, so you might excite some transient. If you've gotten it to work accurately and you've tested it then I won't tell you to not use ferrites, but those are things to think about when using inductive components as they might create a challenge with measurement.
It is a common practice and practical to use single voltage source for multiple loads or components (FPGA, MCU, buffers, etc.) to save on cost. The ferrite bead is effective at reducing the coupling of noise from other switching loads in the same voltage rail. The capacitor is placed right after the ferrite bead to reduce or counter the impedance introduced by the ferrite bead. However, this setup sometimes causes a small amount of oscillations across the capacitor if the values are not properly selected. Sometimes, it is better to use a small value of resistor instead of ferrite bead.