Why do we consider PMOS as pull up and NMOS as pull down transistor

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  • เผยแพร่เมื่อ 18 ต.ค. 2019
  • This Lecture deals with concepts of Pull up and pull down network in a cmos technology.

ความคิดเห็น • 30

  • @mrinalkantidebnath3046
    @mrinalkantidebnath3046 3 ปีที่แล้ว +6

    You explain it simply , keep making such video.

  • @clementdidier6624
    @clementdidier6624 3 ปีที่แล้ว +6

    That's the explanation i was looking for !

  • @irfankanth368
    @irfankanth368 3 ปีที่แล้ว +2

    Brilliant lecture !

  • @princeverma-or7nc
    @princeverma-or7nc 3 ปีที่แล้ว +2

    Thank you sir

  • @khushalkhan1449
    @khushalkhan1449 2 ปีที่แล้ว +1

    Great 👍👍👍

  • @aiswaryamohan8158
    @aiswaryamohan8158 3 ปีที่แล้ว +4

    Nice lecture , thank you

    • @semitech01
      @semitech01  ปีที่แล้ว

      Thank you. Stay connected for more videos on electronics

  • @bharatsuthar963830
    @bharatsuthar963830 2 ปีที่แล้ว +1

    Superb concept sir...

  • @constantkim3155
    @constantkim3155 4 ปีที่แล้ว +3

    thank you for your nice lecture

    • @semitech01
      @semitech01  ปีที่แล้ว

      My pleasure:) stay connected for such videos

  • @skireeti5279
    @skireeti5279 4 ปีที่แล้ว

    Thank you

  • @ayushbachan6113
    @ayushbachan6113 2 ปีที่แล้ว +4

    brilliant, i was solving by attaching drain to Vout here also, which is wrong

  • @FalakSoomro
    @FalakSoomro 4 ปีที่แล้ว +1

    nice

  • @guttaumasankar8909
    @guttaumasankar8909 หลายเดือนก่อน

    I didnt gey why output wont depends on Vt when NMOS connected in Pull down network ?? !!!!!!!

  • @215_raveenchandra8
    @215_raveenchandra8 3 ปีที่แล้ว +4

    Why for cmos we use capacitor to take the output????
    while in bje we generally use a resistor

    • @semitech01
      @semitech01  3 ปีที่แล้ว +6

      If we look at the very purpose of designing any CMOS ....It is nothing but to deliver a clean 0 (logic 0)and clean 1(logic1) at the output , which we can say , is also foundation of a designing a complementary MOS (NMOS+NMOS) which serves the idea of having rail to rail complementary logic which inturn delivers lower power consumption in CMOS as compared to BJT.
      Capacitor at the output in CMOS helps to store clean 0 and 1 . So serves the purpose of low power consumption in the device which cannot be seen with resistor at the output.
      On the other hand BJT is preferred in the scenario where high switching speed is required.BJT serves this purpose by having resistance at the output. RC delay is not predominant in BJT due to absence of capacitor at the output.
      To conclude , I would say one of dominant factor for resistor being at BJT output and capacitor at CMOS is to serve switching speed and rail to rail complementary logic in BJT and CMOS respectively.

  • @VikasYadav-ju9qv
    @VikasYadav-ju9qv ปีที่แล้ว +1

    Nice job

  • @shivankitss8396
    @shivankitss8396 3 ปีที่แล้ว

    Wow grape 🍇. Thanks

  • @raviiitn7405
    @raviiitn7405 2 ปีที่แล้ว

    brilliant sir

  • @saurabhsharma-ry9cw
    @saurabhsharma-ry9cw ปีที่แล้ว

    Nice one

  • @danieltambunan9717
    @danieltambunan9717 6 หลายเดือนก่อน

    2:35 why do we need to increase Vgs?

    • @semitech01
      @semitech01  6 หลายเดือนก่อน +1

      In general, Vgs controls the current in the MOSFET . So, with the increase in Vgs current increases and thereby output voltage decreases.
      But to give a context how we can achieve the maximum output voltage when we consider PMOS as pull down. I said if we increase the Vgs output decreases so we have to decease the Vgs to get higher Vo up to an extent that PMOS stays ON. which is when Vgs=vt . That gives the maximum output of VDD-Vt.
      Hope it helped !

  • @rajathravi7624
    @rajathravi7624 4 ปีที่แล้ว +1

    ಈ ಸಲ ಕಪ್ ನಮ್ದೆ...!!