CMOS Logic Gates Explained | Logic Gate Implementation using CMOS logic
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- เผยแพร่เมื่อ 15 มิ.ย. 2024
- In this video, the CMOS logic gates are explained. By watching this video, you will learn how to implement different logic gates using CMOS logic gate.
CMOS stands for Complementary Metal Oxide Semiconductor. The CMOS logic gate consist of complementary pair of NMOS and PMOS transistors. The NMOS transistors are used in the pull-down network and PMOS transistors are used in the pull-up network.
In the video, it is also explained that , why PMOS transistors are used in pull-up network and NMOS transistors are used in pull-down network. And at the later part of the video, the power consumption of the CMOS logic gates is also briefly discussed.
By watching this video, you will learn the following topics:
0:00 Introduction
0:48 What is CMOS ?
3:12 NMOS Inverter and Issue with NMOS transistors
7:05 Why NMOS passes weak logic '1' and strong logic '0'
9:17 Why PMOS passes weak logic '0' and strong logic '1'
11:48 CMOS Inverter (NOT gate using CMOS Logic)
16:04 NAND and NOR gates using CMOS logic
20:35 AND and OR gates using CMOS logic
21:40 XOR and XNOR gates using CMOS logic
25:29 Power Dissipation in CMOS logic gates
For notes on CMOS logic gates, check this article:
bit.ly/CMOS_Logic_Gates
For more videos on Digital Electronics, check this playlist:
• Digital Electronics
This video will be helpful to all the students of science and engineering in understanding the CMOS logic gates.
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Music Credit: www.bensound.com - วิทยาศาสตร์และเทคโนโลยี
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For Notes on CMOS Logic Gates, check this article:
www.allaboutelectronics.org/cmos-logic-gates-explained/
For more videos on Digital Electronics, check this playlist:
bit.ly/31gBwMa
I made video on this CMOS a year ago.. But hats off to you... I just wish I could provide explanation like you
The most relatable video on youtube to the point and this is perfection......................sir love you and thankssssss 🥰
Exam in 4 hours and the professors notes were so confusing, thank you so much for this video I understand everything I needed within 15 minutes T-T
This lecture is really helpful and much easy to understand 🤩
best and very much helpful vdo.....thanks a lot☺
Definitely you are the amazing tutor 👌🏻👌🏻
amazing video thank you very much!
Absolutely superb
Brilliant explaination🙏
Very well explained
very helpful video,thanks
very good explanation
Thank you ❤️
thank u very much sir
Amazing video
22:26 , sir there is one more representation of xor gate that is possible in which we have PDN network in series form only, pls make a short video on that comparing that representation with this one,
Yes, will try to cover that too.
@@ALLABOUTELECTRONICS sab cover kr lo jai mahakal!
but there must be a connection between source and drain right 4:03 (you only showed voltage between gate and source),you have not showed in this video or am i wrong
at 4:23 you say the output voltage when the mosfet is open is 5vs. how is that possible to be 5vs with the presence of a resistor?
Sir arrows waale pmos cmos use krlo pleaseee
Sir please make playlist on ic 8051 and ic 555
555 is already covered in detail, please check this playlist for more information.
th-cam.com/play/PLwjK_iyK4LLCVdgBR30pSFVj-17TI_8ou.html
@@ALLABOUTELECTRONICS thankyou sir for this help^_^
What happens when we connect Vdd to nmos and vss to pmos ??what will be the output
Nmos and pmos will be always on
Sir I have one doubt how pmos is pull up network and nmos is pulldown network
When PMOS is ON, it will connect the output node to VDD. So, it will pull-up the output voltage to VDD. (That's why its called pull-up network) On the other hand, when NMOS is ON, then output node will get connected to the ground via NMOS transistors. So, we can say that, the NMOS transistors are pulling down the voltage at the output node to logic'0'. (And that's why they are called pull-down network)
I hope, it will clear your doubt.
Can you please explain why your ignoring bar(‘) and writing A.B While constructing NAND gate. How the bar(‘) operation takes place here
Would you please mention the timestamp where you are referring to in the video ?
15:14 here if arrow denoting outside means p channel and inside means n channel but you done opposite here how it is acceptable
It is other way around, the arrow going outside denotes n channel and arrow going inside denotes p-channel. The upper one is p-mos and lower one is n-mos transistor.
@@ALLABOUTELECTRONICS sir thank you for your reply so that means it is your assumption right?
Mosfet exists in depletion and enhancement mode, for depletion it is similar as jfet, for enhancement mode it is opposite to that
sir can we get pdf of the complete playlist
its really good but pls don't speak with an Indian accent its really hard to understand ;)
There are subtitles if you don’t understand. A person cannot change the accent from one day to another. Stupid comment
so beacuse of you only, he should change his accent, cmon he is teaching for free on youtube
I have no issue with his accent.
But stating he is doing this for free, is incorrect. A channel of 600k subs, earns quite a big buck.
I already finished this course when i commented. why would i ask for myself are you stpd. I commented this in everybodys behalf so its easier to understand in his future videos...
Ofc lets believe the subtitles are correct 👏👏👏😮💨
Thank u sir