Simulation result is wrong for example module stimulus at 4:14 since 25 units time delay is assigned for b and y but 30 and 35 are came out of nowhere in simulation result!!
This is because within an initial block, the delays are compounded. So in the first one, "a = 1" executes at time 5, then "b = 0" executes 25 units of time after "a = 1" executes, 5 + 25 = 30, therefore "b = 0" will execute at time 30. The reasoning is the same for 35 in the second initial block.
1) Is Parallel Block and Fork-Join are same?
2) In between Fork-Join if delay time is not mentioned, is all the statements completes at time 0?
Simulation result is wrong for example module stimulus at 4:14 since 25 units time delay is assigned for b and y but 30 and 35 are came out of nowhere in simulation result!!
This is because within an initial block, the delays are compounded. So in the first one, "a = 1" executes at time 5, then "b = 0" executes 25 units of time after "a = 1" executes, 5 + 25 = 30, therefore "b = 0" will execute at time 30. The reasoning is the same for 35 in the second initial block.
Mam thank you so much. Nice explanation 👌.
Thanks Giridesh!
From 20:00 to last screen is blank, ultimately u vl given explanation
When we are declaring Q in output declaration why we are defining output as reg again, why not inputs as net here?
In always and initial blocks Left hand side variable should be reg and right side variables may be reg or net
@@durgaprasadmaddala3727 sir what is' nested ' meaning here
Telegram link is expired....please upload again
how to write testbench for it
I'm going to upload a dedicated video on test bench writing, there you will get all the concepts.
Stay connected and keep supporting ✌✌
@@vlsipoint thanks
why we are putting( Q+1)%16 in 4 bit binary counter
Q=q+1 is to count it from 0 to 15 as it is a 4 bit counter it has to stops at 15 and count from 0 so we are taking modulus of 16.
Mam in 10:5 you said the time u it's is 10 but the time units is 5 only
what is the difference between initial and always?
In intra assignment delay you said 10
But it is 5
Hello Ma'am!!
Please can you make a series on VHDL Language too!!
unable to join telegram group mam and please upload some videos for test bench and some codes for some tough digital systems
Non-blocking statement not clearly explained. More examples would have been better.