IntroductionToVerilog Part2

Behavioral description of digital circuits in Verilog using continuous assignments and procedural assignments like the if-else statement. Introduction and use of always blocks. Hierarchical design using Verilog to implement 1-bit full adder with 7 segment display.

[@Chloeinwonder1and_]

This is the best Verilog beginner tutorial I’ve found so far by a huge margin, this was amazing! Thank you so much

[@gilbertmiao8662]

Still, in 2021, the best Verilog tutorial for beginners. Thank you very much!

[@aliaijaz5571]

sir your work is extra ordinary i don't have words to praise your quality work

[@alecsei393ify]

Thank you so much for the content, very good and well explained,
but where is the part 3, 4 of this series?

[@jr.shivendra4271]

Basics are explained very precisely.....But i found it on last night of my exam

[@vksalian]

Thanks for the good tutorial video, sir.

[@RustyTube]

Very good, clear and concise. Thanks! 😉

[@zachjackovich116]

thank you, great explanations

[@Qiq-og6ms]

Thank you so much! Very well explained

[@anamaykane9355]

Could the statement c = a&b have also been written in the always block?

[@elwafi2001]

Very good lessons

[@kharazmkharazmi8236]

really thank you for good tutorial
the god protect you

[@juexuanzhang7499]

Thank you so much ;

[@pouya6768]

thank you!

[@parkerd2154]

about how many logic cells would a full adder like this use in an standard Xilinx FPGA?

[@yck3810]

Can I ask that the x1, x0, in FullAdd_Display module are the s and c2 in the previous FullAdd module?

[@santhoshsabbella1168]

thank you very much sir.

[@zhenbiaoli5196]

Thank you!

[@mansid7676]

Sir, are you using digitial design using verilog by Stephen brown as reference ?

[@BADKALOS]

Thank you. Really helpfull !

[@nohamazenhussein4788]

thanks sir

[@conman2317]

What does register do?

[@dineshramkumar8177]

They store values in them

[@PreludeSon]

I thought the convention is function(output, input, input...etc). But, I'm seeing X0 and X1 as output but Cin is also output. Maybe it's just me -- it looks like this is just inside a module and has not yet completed as a whole in terms of code.