Excellent tutorial for introducing both Verilog and modelsim. Didn't waste my time with an hour of pointless pre-theory and jumped right into showing practical applications. Thank you very much!
Hello Peter, I just bought a DE2 Ed and Dev Board Kit (Outdated but a great board to do everything on!) and started learning about VHDL with the Altera tutorial about a month ago and found out that it was getting over my head very fast. Then I discovered your Intro to Verilog and ModelSim videos. I have had more success with your training! I have successfully ran the and_example.v and and_struct.v projects and now more knowlegable in the process! Your training has made me more knowlegable on Verilog in 3 days and i'm for now using it as my programming language. So thank you for pointing me in the right direction and I hope you have more videos for using my hardware or any hardware for that mater. I now look forward to your training everyday! Thank You again! Barry Selk
Indeed a very enlightening video on Verilog and Modelsim! I learned many things i could not get before, explained in a simple manner. So, thank you very much !
Hello Mr. Peter, I have two push buttons (using Basys2 rev C board) and I want to increment a register (counter) when i push one of them .I used : always @( posedge pb1 or posedge pb2 ) begin if(count2==9) count2=0; else count2= count2+1; end but when I implement it (using ISE 9.2), an error appeared: ""The logic for does not match a known FF or Latch template. "" So why this happened? and when I used one event (posedge pb1) , it worked ! Thanks
Hey everyone, unfortunately when I run the simulation no instances are created in the and_struct_tb (there's no plus to its left), and no objects are created, did anyone notice this problem? I followed the exact steps.
initializing a two bit register to -1 would imply it's two's complement. Yet it increments like an unsigned register. I find that confusing. How should I think about it?
Error: (vsim-3033) D:/TECHNICAL/Embedded_Systems/SOFTWARE/VERILOG/simple_project_with_modelsim/and_struct.v(9): Instantiation of 'NOT' failed. The design unit was not found. # # Region: /and_struct_tb/MUT # Searched libraries: # D:/TECHNICAL/Embedded_Systems/SOFTWARE/VERILOG/simple_project_with_modelsim/work # Error loading design I get this error. Could you tell me why? Thank you
Thank you Peter for teaching me Verilog! Your tutorials gave me a solid foundation that I’ve used in my every day work. Thanks again!
Excellent tutorial for introducing both Verilog and modelsim. Didn't waste my time with an hour of pointless pre-theory and jumped right into showing practical applications. Thank you very much!
Hello Peter, I just bought a DE2 Ed and Dev Board Kit (Outdated but a great board
to do everything on!) and started learning about VHDL with the Altera tutorial
about a month ago and found out that it was getting over my head very fast. Then I
discovered your Intro to Verilog and ModelSim videos. I have had more success
with your training! I have successfully ran the and_example.v and and_struct.v
projects and now more knowlegable in the process! Your training has made me
more knowlegable on Verilog in 3 days and i'm for now using it as my
programming language. So thank you for pointing me in the right direction
and I hope you have more videos for using my hardware or any hardware for that
mater. I now look forward to your training everyday!
Thank You again! Barry Selk
Thank you professor.
Because of you, someday someone who watched your video will solve NP=P problem :)
Indeed a very enlightening video on Verilog and Modelsim! I learned many things i could not get before, explained in a simple manner. So, thank you very much !
Best Verilog introductory tutorial on youtube.
Hi Peter,
Thanks for the great tutorial.
If you are a beginner like you installed Modelsim today, this is for you. I can't Thank you enough @Peter for this.
Awesome tutorial! Thank you!
Amazing toturial !!!
Hello Mr. Peter,
I have two push buttons (using Basys2 rev C board) and I want to increment a register (counter) when i push one of them .I used :
always @( posedge pb1 or posedge pb2 )
begin
if(count2==9) count2=0;
else count2= count2+1;
end
but when I implement it (using ISE 9.2), an error appeared:
""The logic for does not match a known FF or Latch template. ""
So why this happened?
and when I used one event (posedge pb1) , it worked !
Thanks
Hey everyone, unfortunately when I run the simulation no instances are created in the and_struct_tb (there's no plus to its left), and no objects are created, did anyone notice this problem? I followed the exact steps.
Excellent
Thank you!
initializing a two bit register to -1 would imply it's two's complement. Yet it increments like an unsigned register. I find that confusing. How should I think about it?
Thanks a lot
Why is vhdl status has a question but mine is a X mark? I have problem compiling the vhdl file. It shows # Compile of AND2.vhd failed with 1 errors.
thank you •ᴗ•
Thank you peter
Hello Mr. Peter , could I ask you about some problem in my code in verilog?
why not "count
i think the "
Write a VHDL program to describe the following combinational circuit
"AP-is-troff"... it's pronounced "ap-OS-tro-fee"
Error: (vsim-3033) D:/TECHNICAL/Embedded_Systems/SOFTWARE/VERILOG/simple_project_with_modelsim/and_struct.v(9): Instantiation of 'NOT' failed. The design unit was not found.
#
# Region: /and_struct_tb/MUT
# Searched libraries:
# D:/TECHNICAL/Embedded_Systems/SOFTWARE/VERILOG/simple_project_with_modelsim/work
# Error loading design
I get this error. Could you tell me why? Thank you