I've seen too many people comparing nm directly and saying Intel is far behind, it's great to hear an actual explanation. I also love to see that as we reach atomic scale, engineers need to be creative and change the geometry of the transistor. From planar to FinFET, to Gate All Around and more.
I was thinking about the atomic scale of the chip designs, never made a move to check it out. How can we print UV etched circuits so small? Certainly Heisenberg wouldn't allow that. Interesting to see planar going 3D 🙂 Loved the video.
Maybe a dumb question, but if the gate completely surrounds the substrate, where do the charge carriers go when the field is applied? Is there some kind of skin effect going on? Cause planar FETs push the charges to one side creating a channel near the gate. Those carriers need a place to escape to create a depletion zone.
This is an excellent review of the present fine pitch semiconductor processes. As a retired Analog design engineer, this was a better explanation of many nanometer numbers thrown out by the marketing departments of semiconductor suppliers. Very good graphics as well!
This is by far, IMO, the best electronics technology channel on YT. I often find myself thinking "oh she just covered a point I was wondering about". Anastasi explanations are brief and concise, but packed full of information; it is like her content is the exact opposite of "fluff". Plus to top it off (not that it has any bearing on these subjects) obviously she is absolutely gorgeous .
Anastasi, this is an awesome video because the graphics you used enchanced your explanation greatly. You arrange the flow of the topics very systematically. I was a semicond equipment engineer. I'm amazed by the simplicity of your naration and explained to the comprehension of the lowest assisible knowledge in the field. wow.. congratulations! great job!!
Hi Anastasi! As a bachelor student of Electronics, I cannot thank you enough for this video. I had tried searching for information and distinction on the technology nodes in many books, videos, papers and webpages, but this is where I understood it fully. Thanks!
Anastasi, your subject matter expertise and passion really resonates with how I think and where my interests are. Fantastic channel. Thank you and please don't change!
As a student/researcher with more of an analog/RF background (as opposed to digital like CPU/GPU), the main benefit of technology scaling is increased cutoff frequency. It is the frequency at which the transistor provides unity current gain. Cutoff frequency is a function of transconductance (gm) and parasitic capacitance (mostly Cgs and Cgd). Above this frequency the transistor stops acting like an amplifier. For example, TSMC 180nm has a cutoff frequency of approximately 50GHz meaning that it is not practical to make analog/RF circuits that operate at or near this frequency. The cutoff frequency of CMOS devices continued to increase with technology scaling until 22nm when the cutoff frequency peaked at around 350GHz. In fact, newer nodes like 16nm,10nm,7,etc. have cutoff frequencies significantly lower than 22nm. FinFET transistors have good density for digital circuits but the complex geometry adds undesirable parasitics at high frequencies. Chip are most commonly made in CMOS but other materials like GaAs or InP have carrier mobility that far exceeds that of CMOS, leading to much faster transistors and better analog/RF qualities. Although non-CMOS technologies are far less dense (like 100K transistors/mm^2 instead of 100M/mm^2). Perhaps heterogenous integration will be necessary in the future to continue improving analog/RF performance. You could have the density and Moore's law scaling of CMOS with III-V transistors for RF that have very good high speed performance.
Lachlan, thank you for your comment. Indeed FinFet is not really made for RF and even more not suitable for mm-wave applications, for reasons that you mentioned and also for cost. Most of RF/mm-Wave circuits do not scale with tech nodes and thus getting more and more expensive with each tech shrink. 22nm CMOS will likely be the RF sweet spot for the next decade. On the other hand we will see more CMOS + III-V integrations in e.g. SiP for those RF/mm-Wave applications where RF power is important.
Very interesting. I'm only a technician but would I had the choice, it's something that I would have like to study more. But I'm too old now, so I watch these videos instead and try to learn as much as I can. Also, english isn't my language.
@@MarvinHartmann452 You are the only one . I am also in your status. I don't know what is your story, but me, I wasted my life away. The only thing I can do now is to learn as much I can to satisfy my curiosity. Good luck to you, sir.
They should go for transistor count per square or cubic micrometer. Would be the easiest to undrerstand for everyone, and would be more telling of the actual performance. And as a bonus, it would rise continuously as technology progresses.
You’d already know what it means if you have a computer science background or if it’s relevant to your profession. Most normal people don’t care about specs, they care about price which usually corresponds to the chip model age and performance.
@@H53. Actually no. This would describe an industry standard for creating specs. It would be for everyone, not just Intel. It would make less sense otherwise (nothing to compare, so why list).
I am totally clueless when it comes to the inner circuits of machines and yet I understood most of your explanations. You're great I hope you're a teacher, thanks for your work!
🙏🙏🙏🙏🙏🙏 with 45 years in heavy & marine engineering also production machining.., I have but some appreciation of your industry and the accuracy & precision…., it blows my tiny mind…👍🙏🙏🙏 And you are so youndg👍
I hope the industry moves to transistors per square millimeter sooner than later. That's a measurement that doesn't allow the marketing department to get too creative. It also directly tells the usable transistor count instead of some measurement that cannot be interpolated over big areas.
It is always good to put low pass filter on "vocal" stream and also cut some excessive high mids frequencies with equalizer to make speech more accessible to the listener... tons of information from this great channel are worth it
She cuts mids and hi's, speaks like whispering, I resemble transsexual voice features, breaking in the process the male/female recognition system of a brain rated IQ 160. Now, the question is (I know it sounds cheeky and undesirable): "Anastasi in Tech" is a he or she?
@@dosdoktor of course it is nice and very inteligent girl, there might be an issue with vocal cords/larynx it happens.. Great channel, she is really "horny" on hi tech... I mean it's her real passion, I admire her :)
Amazing that this video is promoted to me by youtube a year after it was released. A sign of quality content. When I was a kid in the 90's I somehow got intel to send me technical manuals about it's latest CPUs... I thought they were cool but above my head. Well I ended up in software/web development at age 16 and since but I've always been fascinated by the silicon innovations underneath. Thank you Anastasia for giving us a peek into the physics of it all.
Sorry if I misspelled your name too, despite knowing the greek root of it means "resurrection". Just putting it out there; "dead" languages are still useful to know!
Wow! I had no idea the dimension had just become a marketing gimmick! I hope you'll make a video explaining what IBM's analog AI chips are and how they work. Thank you, Anastasi.
Most interesting, especially where you explain in detail about the nanometer debacle, which many people unfortunately still confuses! You're beautiful, thanks!
Great explanation as always. Idea for another video : explaining how logic density differs from SRAM/cache and Analog/( I/O) density from different manufacturers as well. Also multiple layers of EUV and MASK. Also core to core interconnect like ring or mesh formation effecting power consumption. Like even on Intel7 Intel chip using 50% more power than AMD on 7nm. Last but not least, manufacturing of DRAM and VRAM, why they are stuck on 10nm. Thanks!
Anastasi in tech, Very nice explanation of the details of the various benefits of the size of gates an various thickness effecting capacitance and therefore switching frequencies! Nice tech talk and well presented! I love your Italian/ Austrian accent is actually is pleasant to my American ear. I have subscribed and watch your other posted videos! I was wondering what school you did your studies! Obviously, you are doing quite well in the field! Marketing is evolved with sales besides engineering and have different motivation and direction!
I gotta apologise, I really didn't give you a chance, because I really thought you were just someone reading a script and another pretty face. I know, I know I was being stupid. I should know better, people hear my voice and assume I'm stupid with my southern draw. Starting to think they may have been right. Haha. From now on I'm gonna give this channel a chance, great info really answered allot of my questions on how cpu's are made. Recently got back into gaming after a long stint on consoles. I forgot how cool pc really are. Loving learning again, building new computers. Just finished my third gaming PC. And starting on a my first DIY cooling PC. Went with a 13700k and a 3080 I had laying around with no cooler. Although I'm really liking the new look on the 7900xtx ref. Sorry sorry I tend to ramble. Anyway great video thanks.
Hi Anastasi, first of all ..... Thank you so much for this great information that quenches most laymen's curiosity about wafers especially on the nanometer terms... Thank you so much... 2nd of all, you are so beautiful yet so intelligent! Thank you so much for this contribution into this complexed semiconductor world.
I would love to see a video explaining and comparing different gate types what are used. Like apple m1 chip, amd ryzen and nvidia gpu gates if they have similiar or different gate types and how it affects batterylife and powerconsumption. Love your videos, style of the videos and overall feeling🤘🏼
that, and why the newer smaller nodes nvidia and some others are using are doubling or more in power consumption. is there a limit of sorts where power saving ends/no longer scales as it did due to issues with the nodes getting so close to that quantum limit?
@@Joe-Dead, The power used is proportional to the number of transistors, the capacitance of each transistors and the clock rate. The capacitance of each transistor is related to the physical size of the transistor. It used to be as the number of transistors per chip increased, the size of each transistor decreased. As explained in this video, this is no longer the case. Now, as the number of transistors per chip increases, the size of the transistors grow in the vertical direction so that the actual size of the transistors doesn’t shrink.
@@terjeoseberg990 that doesn't actually answer anything. smaller process nodes have TRADITIONALLY shown an increase in efficiency. IE, less power used and less power wasted as heat. then you have nvidia using tsmcs smallest nodes and DOUBLING power consumption. it's not just more transistors, i know how that works...pretty obvious more parts = more power needed. even with the savings from efficiency using smaller nodes. while the power draw was going down it went WAY up. you'd expect that kind of doubling if they doubled the amount of transistors as well...well doubled and added a bit more since you have to count for efficiency from smaller nodes as past node changes had produced that efficiency at an almost predictable scaling. one thing you did not mention and i felt i had no need to...the power consumption could just be down to how they designed it...but why would you design such an absolute power hog? when the trend has been towards efficiency? sipping instead of mainlining current.
@@Joe-Dead, Actually, my answer does answer the question. You obviously don’t understand it. The capacitance of a transistor increases with the size of the transistors because the transistor looks like a tiny capacitor. And if the capacitance is greater, it takes more current to switch the transistor on or off. It also switches slower. That’s why the clock rates stopped increasing and why the power usage has increased. There is no longer a reduction in capacitance and therefore current with smaller node technology because the transistors are no longer getting smaller.
@@Joe-Dead, If you don’t understand what I’m saying, watch this video again. She explains what I’m saying in this video. The transistors might be getting narrower, but they are simultaneously getting taller, and therefore they are not getting smaller.
The microprocessor industry is nothing short of magical. You can explain it down to the lowest details but in the end you just have to accept how it simply works. Like how billions of transistors can produce a computational task. It truly takes an incredible mind for anyone to be working in designing these chips. This is the pinnacle of human ingenuity
"Architects" and managers do not design the chips, the process/materials physicists/engineers who elect to pursue and open up the pre-existing design options do. The many 3D geometries have been around for a couple decades.
Super interesting! The marketing folk had confused me, but I like to look at power in & performance out which makes me immune to a lot of the marketing. Still lovely to get more clarity & information. Thank you for sharing!
Hello. This video was really good if somebody would like to a know a little bit more from process nodes. You've made a little mistake. Originally a process node as you told, showed that how long the gate in the actual transistor. But much more before FINFETS there was a little change. In 1997 or 1998 when Intel moved from 350nm node to the 250nm node. At the 250nm node the gate lenght was much smaller (190-200nm) because the engineers dircovered a method how to shink it's size more smaller than other parts. And from that node until the 32nm (Intel's last Planar FET node) it was defined also something else. A measure was adverts to a size of a group of transistors. Anyway your videos are real good. I'm impressed. (I've first seen TSMC - ASML ) And your hair is really nice. ;)
Constructive feedback Your English is very good, just need to listen to yourself when you say the word oxide, it sounds very much like exit. Your video is great in helping people advance in the fast expanding world of technology and hardware 👍
It's amazing how tech has progressed over the years. Thank you for your wonderful explanation, it makes modern computer technology easier to understand for an oldie like me :-)
I had been working in TSMC fab3,4,8 for 8” wafer 20 years ago. By the time fab12 had been built for 12” wafer manufacturing for the first one, and I was also inside of it. My brother is currently in one process of 3 nanometers manufacturing. Thank you for your acknowledgment.
Thank you for the explanation! I remember the spec race in Hi-Fi equipment by Japanese companies vs NAD musical output from music medium like Vinyl,CD, Cassette. Maybe that was a bad comparison but I was thinking according to marketing process to sell products. Yes , I use NAD Audio devices.
You surely remember the power war of the late 70s/early 80s, too. I used to have many different brands of systems. I do like Nad. I think m Mcintosh also makes awesome systems, Accuphase is quite good, too. There's so many of them that are good.
I love the content here! Feedback: is there a way to change the microphone/ audio settings so there is not too much treble? The letter S sounds extremely low while the rest of vocalizations are 3x lower? Its minor but it would help the overall sound quality…
When you said if we want to know more about FINFET and other technologies and pointed 👉 to the video there was no link. Just letting you know since I'm interested. Thank Anastaci. You are great 👍
I know you mostly cover the "hardware" side of things BUT would you ever consider doing a video covering: Where we are at with our ability running physics simulations? I really find physics rendering so facinating and I'd enjoy anything covering physics based advancements or creative ideas related to this topic.
Came for your amazing hair(you could easily have this sponsored by a hairproduct brand), stayed for the information. So clear of an explanation! Thank you
Being a guy with military background, I am interested in how transistors used in modern IC gates respond to EMP attacks. Back in the early days it was discovered that cmos gates in integrated circuits were susceptible to damage in high voltage situations such as static where very low current is found with very high voltage. I'm wondering if the military transistors have found ways of getting around EMP attacks as transistors have become smaller and smaller, eventually breaking the 1nm barrier. The only way i know of is to use TTL instead of FETs,
CMOS has been rad hard for over 40 years...back in the 80's, and still today, rad hard devices were made on SOS wafers. A SOS wafer has a wafers made of sapphire and an episilicon layer deposited on the top surface. The active trasistor regions are defined in the epi layer and there is no connection between the p and n channel areas to allow for lockup. Buried oxide layers like AMD used also produced the same effect, not sure about the TSMC process. Another way of producing rad hard devices is to implant highly doped buried layers that 'sweep" and current from an ionising event away from the transistor areas to junctions where the charges can recombine safely. BTW here are a couple of papers that detail EMP effects, if you are interested: www.researchgate.net/publication/310582078_Latch_up_effect_under_electromagnetic_pulse www.researchgate.net/publication/296683413_The_Induced_Physical_Effects_on_the_Semiconductor_Electronics_under_Electromagnetic_Pulse You can download the full paper.
Since the interconnect delay is starting to dominate the switching time, packing transistors closer together will continue to reduce the interconnect delay time portion of the overall switching time, but the increase in physical size of the 3D transistors might make that a wash.
Well, as a chip designer it has been 'routing>logic' delay since going below 1um. So 3D transistors halving routing delay would be a massive advantage, I see a future where the transistor could get larger but stacked three layers deep, the biggest problem then becomes heat...
Great summary thank you. I wasn't aware of that gate thickness was already reaching quantum mechanical limitations (30A), and that this would slow down gains in power efficiency.
Pitch is the usual measurement of the density, ie how close together pairs are. For example true dense is equal line & space, if you can build transistors that close together they are really dense. You might only be able to print them, say 2x the line size, so a 100nm transistor can only be placed every 200nm. That is a simplistic and sort of unrealistic explanation but gives you a good idea. Also the smallest pitch of backend metal connections has a big impact on how large the die is, it isn't just what you can do at the transistor layer...
Hi, you know so much about semiconductor technology, you must be quite highly qualified and working in this field, it would be interesting to know more.
If gate length is not expressive anymore, I'd switch to transistor density (transistors per square mm for example). Further minimizing of structures amplifies the problem of leakage currents, quantum noise/tunneling effects and high frequency interference. With focus on the first aspect, shrinking down only helps if efficiency raises in the same scale. When facing current GPU development (take RTX 10xx to 40xx series) in terms of power consumption, it seems half of the electrical energy dissipates through leakage already - manufacturers move towards producing overpriced power resistors, so to say. To conclude, at 5 nm we might approach the rational limit for Silicon-based chip technology - we're talking about the width of 50 atoms btw. For more downsizing towards 1 nm and below, let's rather find better materials and production technologies.
1:00 Even a non tech will understand how this works. What I know before is chip like a playground the smaller the faster rounds you make. Now, I have more info. Thanks
In my ingenuity, I was thinking "oh, the nanometer in the nodes is the precision that they can create every part of the transistor " but now I know that I completed misunderstood everything.
Wow I feel old. I remember people saying we cant go below 1um transistors with current lithographic techniques. The original 6502 (earliest CPU I have worked with) was 8un technology way back in 1975.
Thanks this is very helpful! Wonder will we reach a stage where the benefits of technology scaling are outweighed by the higher costs and the less benefits of incremental performance. Welcome any thoughts.
Hahah cute cat, also a very interesting topic! I always wondered, there is a physical limit to where electrical currents can just pass through materials sufficiently small
4:40 correct is a marketing number, I learnt this in the course of Nano electronics and semiconductor technologies I commented you about in other of your videos, I hope you have read it! I did not check my YT notifications because sometimes I receive many and ones shift others :(.... 5:58 Power is not just I*V, is static and dynamic power, static is the leakage of the transistor in an "OFF" state and dynamic yes comes from I*V but is = f*C*V^2, so it depends on speed (frequency), Capacitances and yeah as you said Voltage supply. 6:46 for the new people in this nano world, GAA = Gate All Around, is the Gate going around all the channel, not just above and sides as FinFET's 😉..... 6:58 exact but reducing the gate oxide thickness can also lead to problems like leakage through the gate so is not so good.... 8:50 nice that you mentioned interconnect.... 9:00 cool that you mentioned the PAA... 10:24 Intel inside! :D.... 11:14 yeah you now said it! PPA, now you miss 2 factors, C and E.... 11:55 EUV = expensive XD so yeah you mentioned C = Cost there, you missed E.... 13:16 hahahah water 🤣😂💚... 13:34 I did not see the link :( of VFETs.... Waving you from Brussels Anastasi!!! ❤💚💚🤗🤗 ciao chau chus a bientot! tot ziens! 😚😘😊💚💚
I've turned on my Mackintosh Plus in virtual flopy drive mode, while watching this episode :p Thank you for knowledge you give Anastasia (ΑΝΑΣΤΑΣΙΑ) :-)
So, the smaller they are, the higher the bandwidth, the lower the voltage. Interesting, it makes sense. I'm only a electronic technician, I'm not a mega genius like the people this video is directed to, but it's very interesting.
Let me know what you think !
Your the best ,All rolled into One!
YOU ARE LOVE 💕
Somebody should start comparing nodes with transistor density.
Pienso que eres HERMOSA!!!!
i want -1 nm cpu for best gaming performance
I've seen too many people comparing nm directly and saying Intel is far behind, it's great to hear an actual explanation. I also love to see that as we reach atomic scale, engineers need to be creative and change the geometry of the transistor. From planar to FinFET, to Gate All Around and more.
You right.
I was thinking about the atomic scale of the chip designs, never made a move to check it out.
How can we print UV etched circuits so small? Certainly Heisenberg wouldn't allow that.
Interesting to see planar going 3D 🙂
Loved the video.
Maybe a dumb question, but if the gate completely surrounds the substrate, where do the charge carriers go when the field is applied? Is there some kind of skin effect going on? Cause planar FETs push the charges to one side creating a channel near the gate. Those carriers need a place to escape to create a depletion zone.
Intel is still far behind 😂
@@Shadow__133 I see you fell for the marketing.
This is an excellent review of the present fine pitch semiconductor processes. As a retired Analog design engineer, this was a better explanation of many nanometer numbers thrown out by the marketing departments of semiconductor suppliers. Very good graphics as well!
Thank you 😊
This is by far, IMO, the best electronics technology channel on YT. I often find myself thinking "oh she just covered a point I was wondering about". Anastasi explanations are brief and concise, but packed full of information; it is like her content is the exact opposite of "fluff". Plus to top it off (not that it has any bearing on these subjects) obviously she is absolutely gorgeous .
This was the boomer post I was looking for. Didn't have to scroll far 😂
Anastasi, this is an awesome video because the graphics you used enchanced your explanation greatly. You arrange the flow of the topics very systematically. I was a semicond equipment engineer. I'm amazed by the simplicity of your naration and explained to the comprehension of the lowest assisible knowledge in the field. wow.. congratulations! great job!!
Thanks a lot😊😊
Yes I'm constantly forwarding her explanations of computing hardware issues to people who get facts from liars or idiots like Peter Zeihan.
Hi Anastasi! As a bachelor student of Electronics, I cannot thank you enough for this video. I had tried searching for information and distinction on the technology nodes in many books, videos, papers and webpages, but this is where I understood it fully. Thanks!
I really though that nm was a real measure for transistors, but your explanation makes much more sense. Thanks Anastasi.
Once the technology became physically too small to actually make for real, they switched to imaginary “equivalent” measurements.
That really stopped at 24nm but even before than many 48nm or smaller nodes where often more an average or guess than actual transistor size!
@@DarthAwar, Right.
Great overview. The numbers are still useful for comparing different chips from the same manufacturer, but not for other manufacturers.
By by by by Dr Dr see we
Anastasi, your subject matter expertise and passion really resonates with how I think and where my interests are. Fantastic channel. Thank you and please don't change!
As a student/researcher with more of an analog/RF background (as opposed to digital like CPU/GPU), the main benefit of technology scaling is increased cutoff frequency. It is the frequency at which the transistor provides unity current gain. Cutoff frequency is a function of transconductance (gm) and parasitic capacitance (mostly Cgs and Cgd). Above this frequency the transistor stops acting like an amplifier. For example, TSMC 180nm has a cutoff frequency of approximately 50GHz meaning that it is not practical to make analog/RF circuits that operate at or near this frequency. The cutoff frequency of CMOS devices continued to increase with technology scaling until 22nm when the cutoff frequency peaked at around 350GHz. In fact, newer nodes like 16nm,10nm,7,etc. have cutoff frequencies significantly lower than 22nm. FinFET transistors have good density for digital circuits but the complex geometry adds undesirable parasitics at high frequencies.
Chip are most commonly made in CMOS but other materials like GaAs or InP have carrier mobility that far exceeds that of CMOS, leading to much faster transistors and better analog/RF qualities. Although non-CMOS technologies are far less dense (like 100K transistors/mm^2 instead of 100M/mm^2). Perhaps heterogenous integration will be necessary in the future to continue improving analog/RF performance. You could have the density and Moore's law scaling of CMOS with III-V transistors for RF that have very good high speed performance.
Lachlan, thank you for your comment. Indeed FinFet is not really made for RF and even more not suitable for mm-wave applications, for reasons that you mentioned and also for cost. Most of RF/mm-Wave circuits do not scale with tech nodes and thus getting more and more expensive with each tech shrink. 22nm CMOS will likely be the RF sweet spot for the next decade. On the other hand we will see more CMOS + III-V integrations in e.g. SiP for those RF/mm-Wave applications where RF power is important.
Very interesting. I'm only a technician but would I had the choice, it's something that I would have like to study more. But I'm too old now, so I watch these videos instead and try to learn as much as I can.
Also, english isn't my language.
There are still a few NMOS and TTL devices. Believe it or not some new designs are still using the 8051!. Not the 80C51 the actual 8051 with EPROM.
Your input is just extraordinary. Thank you for sharing this.
@@MarvinHartmann452
You are the only one . I am also in your status. I don't know what is your story, but me, I wasted my life away. The only thing I can do now is to learn as much I can to satisfy my curiosity. Good luck to you, sir.
Thank you Anastasia for your great videos. I have watched all of them and can't wait until you have the next one up!
Thank you 😀
They should go for transistor count per square or cubic micrometer. Would be the easiest to undrerstand for everyone, and would be more telling of the actual performance. And as a bonus, it would rise continuously as technology progresses.
Yess, its a good idea.
So... Intel should take advice from a YT comment. Got you.
@@H53. agree, not even best advice can help them now.
You’d already know what it means if you have a computer science background or if it’s relevant to your profession. Most normal people don’t care about specs, they care about price which usually corresponds to the chip model age and performance.
@@H53. Actually no. This would describe an industry standard for creating specs. It would be for everyone, not just Intel. It would make less sense otherwise (nothing to compare, so why list).
I am totally clueless when it comes to the inner circuits of machines and yet I understood most of your explanations.
You're great I hope you're a teacher, thanks for your work!
🙏🙏🙏🙏🙏🙏 with 45 years in heavy & marine engineering also production machining.., I have but some appreciation of your industry and the accuracy & precision…., it blows my tiny mind…👍🙏🙏🙏
And you are so youndg👍
I hope the industry moves to transistors per square millimeter sooner than later. That's a measurement that doesn't allow the marketing department to get too creative. It also directly tells the usable transistor count instead of some measurement that cannot be interpolated over big areas.
It is always good to put low pass filter on "vocal" stream and also cut some excessive high mids frequencies with equalizer to make speech more accessible to the listener... tons of information from this great channel are worth it
She cuts mids and hi's, speaks like whispering, I resemble transsexual voice features, breaking in the process the male/female recognition system of a brain rated IQ 160. Now, the question is (I know it sounds cheeky and undesirable): "Anastasi in Tech" is a he or she?
haha i was thinking the same, but, i dunno, theres something with tech and a lot of sssssssssssssssssssssssss´s thats relaxing.
@@dosdoktor of course it is nice and very inteligent girl, there might be an issue with vocal cords/larynx it happens.. Great channel, she is really "horny" on hi tech... I mean it's her real passion, I admire her :)
@@loverschoice885 are you a ASMR fan? 😅
Anastasi! You are one of the most insightful people I've seen on the internet and your videos are very well made! Congratulations and keep it up!
Amazing that this video is promoted to me by youtube a year after it was released. A sign of quality content. When I was a kid in the 90's I somehow got intel to send me technical manuals about it's latest CPUs... I thought they were cool but above my head. Well I ended up in software/web development at age 16 and since but I've always been fascinated by the silicon innovations underneath. Thank you Anastasia for giving us a peek into the physics of it all.
Sorry if I misspelled your name too, despite knowing the greek root of it means "resurrection". Just putting it out there; "dead" languages are still useful to know!
I certainly enjoyed your expertise and presentation in a technical but understandable manner. Loved it !!!
Wow! I had no idea the dimension had just become a marketing gimmick! I hope you'll make a video explaining what IBM's analog AI chips are and how they work. Thank you, Anastasi.
Just found your channel, very interesting, please keep it up.
For the first time I understand a little bit better how finfet transistors work.
Most interesting, especially where you explain in detail about the nanometer debacle, which many people unfortunately still confuses! You're beautiful, thanks!
Thank you Anastasi! Like always you are delivering absolutely great content for us to watch. 👍
Great explanation as always.
Idea for another video : explaining how logic density differs from SRAM/cache and Analog/( I/O) density from different manufacturers as well. Also multiple layers of EUV and MASK. Also core to core interconnect like ring or mesh formation effecting power consumption. Like even on Intel7 Intel chip using 50% more power than AMD on 7nm.
Last but not least, manufacturing of DRAM and VRAM, why they are stuck on 10nm.
Thanks!
Excellent, after all these years i got a real idea about this. Thank you.
I've watched so many videos on this very topic and THIS video is the one that explains it in a way I understand. Thanks for the amazing video!
Anastasi in tech, Very nice explanation of the details of the various benefits of the size of gates an various thickness effecting capacitance and therefore switching frequencies! Nice tech talk and well presented! I love your Italian/ Austrian accent is actually is pleasant to my American ear. I have subscribed and watch your other posted videos! I was wondering what school you did your studies! Obviously, you are doing quite well in the field! Marketing is evolved with sales besides engineering and have different motivation and direction!
I gotta apologise, I really didn't give you a chance, because I really thought you were just someone reading a script and another pretty face. I know, I know I was being stupid. I should know better, people hear my voice and assume I'm stupid with my southern draw. Starting to think they may have been right. Haha. From now on I'm gonna give this channel a chance, great info really answered allot of my questions on how cpu's are made.
Recently got back into gaming after a long stint on consoles. I forgot how cool pc really are. Loving learning again, building new computers. Just finished my third gaming PC. And starting on a my first DIY cooling PC. Went with a 13700k and a 3080 I had laying around with no cooler. Although I'm really liking the new look on the 7900xtx ref. Sorry sorry I tend to ramble. Anyway great video thanks.
Amazing explanation.. no one can explain this simple this complex technology! Great work👏
I learn so much from these videos,
despite the language barrier.
I had no idea. Thank you for clearing this up. It really makes a lot of sense now.
Hi Anastasi, first of all ..... Thank you so much for this great information that quenches most laymen's curiosity about wafers especially on the nanometer terms... Thank you so much... 2nd of all, you are so beautiful yet so intelligent! Thank you so much for this contribution into this complexed semiconductor world.
I would love to see a video explaining and comparing different gate types what are used. Like apple m1 chip, amd ryzen and nvidia gpu gates if they have similiar or different gate types and how it affects batterylife and powerconsumption. Love your videos, style of the videos and overall feeling🤘🏼
that, and why the newer smaller nodes nvidia and some others are using are doubling or more in power consumption. is there a limit of sorts where power saving ends/no longer scales as it did due to issues with the nodes getting so close to that quantum limit?
@@Joe-Dead, The power used is proportional to the number of transistors, the capacitance of each transistors and the clock rate. The capacitance of each transistor is related to the physical size of the transistor.
It used to be as the number of transistors per chip increased, the size of each transistor decreased. As explained in this video, this is no longer the case. Now, as the number of transistors per chip increases, the size of the transistors grow in the vertical direction so that the actual size of the transistors doesn’t shrink.
@@terjeoseberg990 that doesn't actually answer anything. smaller process nodes have TRADITIONALLY shown an increase in efficiency. IE, less power used and less power wasted as heat.
then you have nvidia using tsmcs smallest nodes and DOUBLING power consumption. it's not just more transistors, i know how that works...pretty obvious more parts = more power needed. even with the savings from efficiency using smaller nodes.
while the power draw was going down it went WAY up. you'd expect that kind of doubling if they doubled the amount of transistors as well...well doubled and added a bit more since you have to count for efficiency from smaller nodes as past node changes had produced that efficiency at an almost predictable scaling.
one thing you did not mention and i felt i had no need to...the power consumption could just be down to how they designed it...but why would you design such an absolute power hog? when the trend has been towards efficiency? sipping instead of mainlining current.
@@Joe-Dead, Actually, my answer does answer the question. You obviously don’t understand it.
The capacitance of a transistor increases with the size of the transistors because the transistor looks like a tiny capacitor. And if the capacitance is greater, it takes more current to switch the transistor on or off. It also switches slower. That’s why the clock rates stopped increasing and why the power usage has increased.
There is no longer a reduction in capacitance and therefore current with smaller node technology because the transistors are no longer getting smaller.
@@Joe-Dead, If you don’t understand what I’m saying, watch this video again. She explains what I’m saying in this video. The transistors might be getting narrower, but they are simultaneously getting taller, and therefore they are not getting smaller.
Your voice is sooo soothing, perfect for the subject. Liked and subbed.
The microprocessor industry is nothing short of magical. You can explain it down to the lowest details but in the end you just have to accept how it simply works. Like how billions of transistors can produce a computational task. It truly takes an incredible mind for anyone to be working in designing these chips. This is the pinnacle of human ingenuity
"Architects" and managers do not design the chips, the process/materials physicists/engineers who elect to pursue and open up the pre-existing design options do. The many 3D geometries have been around for a couple decades.
@@kakistocracyusa huh? where did i say that architects and managers design the chips?
@@InnerFire6213 The structural design of chip circuits is commonly referred to as "chip architecture"
@@kakistocracyusa i don't know why you feel like you have to tell me that but thanks
Super interesting! The marketing folk had confused me, but I like to look at power in & performance out which makes me immune to a lot of the marketing. Still lovely to get more clarity & information. Thank you for sharing!
Thanks so much for online classes. We really love science and nanotechnologies.
1:05 "Those are tiny, but very powerful guys". Not sure why, but it boosted my confidence a bit.
Hello.
This video was really good if somebody would like to a know a little bit more from process nodes.
You've made a little mistake.
Originally a process node as you told, showed that how long the gate in the actual transistor.
But much more before FINFETS there was a little change. In 1997 or 1998 when Intel moved from 350nm node to the 250nm node.
At the 250nm node the gate lenght was much smaller (190-200nm) because the engineers dircovered a method how to shink it's size more smaller than other parts. And from that node until the 32nm (Intel's last Planar FET node) it was defined also something else.
A measure was adverts to a size of a group of transistors.
Anyway your videos are real good. I'm impressed. (I've first seen TSMC - ASML )
And your hair is really nice. ;)
Thanks!
Thank you 😊
finally a proper explanation of nm vs design / density, cute kitty and wine glass water was a fun touch, well done
Constructive feedback
Your English is very good, just need to listen to yourself when you say the word oxide, it sounds very much like exit.
Your video is great in helping people advance in the fast expanding world of technology and hardware 👍
Great video and great way of explaining very difficult things!
You are very intelligent and congratulations for the idea!
One of the best common explanation to Nano technology
Awesome video! this is the 1st time I discovered your channel... Your voice is lovely and your explanation was thorough! subscribed
Given this great explanation, I think what we should focus really as costumers is the performance x price and performance x power consumption.
Cats are awesome and yours definitely is one of the cutest I've seen.
Of all the channels, this is the only channel I've had the respect to hit the ringer button for, it always puts me in a good mood, bravo, Anastasia!
It's amazing how tech has progressed over the years. Thank you for your wonderful explanation, it makes modern computer technology easier to understand for an oldie like me :-)
I had been working in TSMC fab3,4,8 for 8” wafer 20 years ago. By the time fab12 had been built for 12” wafer manufacturing for the first one, and I was also inside of it. My brother is currently in one process of 3 nanometers manufacturing. Thank you for your acknowledgment.
Thank you for the explanation!
I remember the spec race in Hi-Fi equipment by Japanese companies vs NAD musical output from music medium like Vinyl,CD, Cassette.
Maybe that was a bad comparison but I was thinking according to marketing process to sell products.
Yes , I use NAD Audio devices.
You surely remember the power war of the late 70s/early 80s, too. I used to have many different brands of systems. I do like Nad. I think m
Mcintosh also makes awesome systems, Accuphase is quite good, too. There's so many of them that are good.
I love the content here! Feedback: is there a way to change the microphone/ audio settings so there is not too much treble? The letter S sounds extremely low while the rest of vocalizations are 3x lower? Its minor but it would help the overall sound quality…
When you said if we want to know more about FINFET and other technologies and pointed 👉 to the video there was no link. Just letting you know since I'm interested. Thank Anastaci. You are great 👍
I know you mostly cover the "hardware" side of things BUT would you ever consider doing a video covering: Where we are at with our ability running physics simulations? I really find physics rendering so facinating and I'd enjoy anything covering physics based advancements or creative ideas related to this topic.
Came for your amazing hair(you could easily have this sponsored by a hairproduct brand), stayed for the information. So clear of an explanation! Thank you
Hair is advanced girl technology. We can't understand. No video can explain it.
Being a guy with military background, I am interested in how transistors used in modern IC gates respond to EMP attacks. Back in the early days it was discovered that cmos gates in integrated circuits were susceptible to damage in high voltage situations such as static where very low current is found with very high voltage. I'm wondering if the military transistors have found ways of getting around EMP attacks as transistors have become smaller and smaller, eventually breaking the 1nm barrier. The only way i know of is to use TTL instead of FETs,
CMOS has been rad hard for over 40 years...back in the 80's, and still today, rad hard devices were made on SOS wafers.
A SOS wafer has a wafers made of sapphire and an episilicon layer deposited on the top surface. The active trasistor regions are defined in the epi layer and there is no connection between the p and n channel areas to allow for lockup.
Buried oxide layers like AMD used also produced the same effect, not sure about the TSMC process.
Another way of producing rad hard devices is to implant highly doped buried layers that 'sweep" and current from an ionising event away from the transistor areas to junctions where the charges can recombine safely.
BTW here are a couple of papers that detail EMP effects, if you are interested: www.researchgate.net/publication/310582078_Latch_up_effect_under_electromagnetic_pulse
www.researchgate.net/publication/296683413_The_Induced_Physical_Effects_on_the_Semiconductor_Electronics_under_Electromagnetic_Pulse
You can download the full paper.
Your videos keep me excited to be creative and give me ideas for new inventions for the near future. Thanks for the inspiration
Since the interconnect delay is starting to dominate the switching time, packing transistors closer together will continue to reduce the interconnect delay time portion of the overall switching time, but the increase in physical size of the 3D transistors might make that a wash.
Well, as a chip designer it has been 'routing>logic' delay since going below 1um. So 3D transistors halving routing delay would be a massive advantage, I see a future where the transistor could get larger but stacked three layers deep, the biggest problem then becomes heat...
Great summary thank you. I wasn't aware of that gate thickness was already reaching quantum mechanical limitations (30A), and that this would slow down gains in power efficiency.
She has Voice thickness of 1 Nano Meter!
Directly touching to My Heart! ❤
Wooow I admit that i love your content is great !!
Your videos are very very good! Very informative and clear!
Enter for the info, stay for the voice!
Just love how she explains technology, thanks
very insightful. this was very knowledgeable and informational video in such short duration. Thank you.
Excellent, thank you Anastasi.
Where is your discussion of vertical transistors?
Here: th-cam.com/video/IHxv8ehrx2Q/w-d-xo.html
Thanks for this easy-to-understand video.
Thumbnail made me wonder why a shampoo ad was mentioning computer chips
Thank you for clarifying the meaning of these numbers. I was always wondering if they are some measure of the density. But obviously they are not.
Pitch is the usual measurement of the density, ie how close together pairs are. For example true dense is equal line & space, if you can build transistors that close together they are really dense. You might only be able to print them, say 2x the line size, so a 100nm transistor can only be placed every 200nm. That is a simplistic and sort of unrealistic explanation but gives you a good idea.
Also the smallest pitch of backend metal connections has a big impact on how large the die is, it isn't just what you can do at the transistor layer...
Hi, you know so much about semiconductor technology, you must be quite highly qualified and working in this field, it would be interesting to know more.
Dude it's her PhD read the intro.
I'll be glad to see the linear, stand-up & applaud!!
Great video and you’ve got a sweet voice 😊
Thank you for making these tech issues understandable and aesthetically pleasing. Ciao.
I would never knew about this without your videos. THANKS😋
很期待intel用tsmc製程，生產最新的cpu，性能將會很強大，希望intel高層能想通，加油。
Intel can't. They will always rely on TSMC for their most advanced and smallest chips.
Great job presenting this! Keep it up...
Perfect explanation, especially charging the gates
Nothing gets as impressive than the 7:59 😻 *switching speed*
If gate length is not expressive anymore, I'd switch to transistor density (transistors per square mm for example).
Further minimizing of structures amplifies the problem of leakage currents, quantum noise/tunneling effects and high frequency interference. With focus on the first aspect, shrinking down only helps if efficiency raises in the same scale. When facing current GPU development (take RTX 10xx to 40xx series) in terms of power consumption, it seems half of the electrical energy dissipates through leakage already - manufacturers move towards producing overpriced power resistors, so to say.
To conclude, at 5 nm we might approach the rational limit for Silicon-based chip technology - we're talking about the width of 50 atoms btw. For more downsizing towards 1 nm and below, let's rather find better materials and production technologies.
Your voice is soothing to the ear🧏🏻♂️
Learned something new today, thanks 🤓
Amazing Video, Thanks!
1:00 Even a non tech will understand how this works.
What I know before is chip like a playground the smaller the faster rounds you make. Now, I have more info. Thanks
Esta foi a melhor explicação que eu assisti sobre a diferença entre os nanômetros dos chips.
Jaxme inscrevi para mais aulas sobre tecnologia
In my ingenuity, I was thinking "oh, the nanometer in the nodes is the precision that they can create every part of the transistor " but now I know that I completed misunderstood everything.
Wow I feel old. I remember people saying we cant go below 1um transistors with current lithographic techniques. The original 6502 (earliest CPU I have worked with) was 8un technology way back in 1975.
Very good video. Excellent explanation and breakdown of complex ideas to easily understandable terms for a normie like me. Lol. Thanks.
Thanks this is very helpful! Wonder will we reach a stage where the benefits of technology scaling are outweighed by the higher costs and the less benefits of incremental performance. Welcome any thoughts.
Splendido video 👍 è il mio patriottismo o alla fine del video ho sentito un " Ciao " ? ahahaha
Hahah cute cat, also a very interesting topic! I always wondered, there is a physical limit to where electrical currents can just pass through materials sufficiently small
You definitely make it sound AWESOME 😁😁😁🦁
4:40 correct is a marketing number, I learnt this in the course of Nano electronics and semiconductor technologies I commented you about in other of your videos, I hope you have read it! I did not check my YT notifications because sometimes I receive many and ones shift others :(.... 5:58 Power is not just I*V, is static and dynamic power, static is the leakage of the transistor in an "OFF" state and dynamic yes comes from I*V but is = f*C*V^2, so it depends on speed (frequency), Capacitances and yeah as you said Voltage supply. 6:46 for the new people in this nano world, GAA = Gate All Around, is the Gate going around all the channel, not just above and sides as FinFET's 😉..... 6:58 exact but reducing the gate oxide thickness can also lead to problems like leakage through the gate so is not so good.... 8:50 nice that you mentioned interconnect.... 9:00 cool that you mentioned the PAA... 10:24 Intel inside! :D.... 11:14 yeah you now said it! PPA, now you miss 2 factors, C and E.... 11:55 EUV = expensive XD so yeah you mentioned C = Cost there, you missed E.... 13:16 hahahah water 🤣😂💚... 13:34 I did not see the link :( of VFETs.... Waving you from Brussels Anastasi!!! ❤💚💚🤗🤗 ciao chau chus a bientot! tot ziens! 😚😘😊💚💚
I've turned on my Mackintosh Plus in virtual flopy drive mode, while watching this episode :p
Thank you for knowledge you give Anastasia (ΑΝΑΣΤΑΣΙΑ) :-)
Terrific videos, thank you for sharing these with the world!
Thank you Anastasi!
Thank you. I find this all fascinating
always love your explanations, thank you
Thank you ☺️
You have earned my subscription. Thank you for the content.
So, the smaller they are, the higher the bandwidth, the lower the voltage. Interesting, it makes sense. I'm only a electronic technician, I'm not a mega genius like the people this video is directed to, but it's very interesting.
I love u so much your generosity and simplicity