DMA basic example

[@umairsaifullah-e2b]

Awesome, keeep up the good work,
Really appreciating you making these designs.
hoping to learn more from you.
I am implementing your designs on Eclypse Z7 board.

[@Udi-FPGA]

Thank you for your comment.
I plan to make more video like this in the future, and I hope you'll find them useful.

[@gnanapradeep2933]

​@@Udi-FPGAcan you please make a video on zynq ultrascale+ mpsoc.

[@Udi-FPGA]

@@gnanapradeep2933 I wish I Could I need an zynq ultrascale+ mpsoc at home for this.
(I'm doing my Videos at home) but I work with mpsoc at work and it is exactly the same. just that the mpsoc have 6 cores and the zynq7000 only 2.
once you put your zynq in the Block design and add something (like DMA) the Autoconnection will work the same.

[@noumanfaheem1928]

Please make a video on custom pl data generation and converting it to axi stream so that it van be input to axi dma

[@Udi-FPGA]

The input to the AXI DMA is a simple AXIS (AXI Stream) bus. It just needs 5 signals: data, Valid keep, last & ready. I explain this bus in the beginning of this video. If you need to write data from the hardware to the DDR you might want to consider the Data Mover IP. This IP is controlled by hardware and transfer data to the DDR without software. (the software only needs to Invalidate the cache one the data was received). I might do a video on this some time soon.

[@noumanfaheem1928]

@Udi-FPGA thank you so much for the prompt response I'll try that tomorrow cheers!

[@elfi2585]

@@Udi-FPGA I made a custom IP that contains some random data for testing, and i linked it to the axi interconnect. I am trying to send fpga data with axi dma to the ps side and then to the ethernet, is it a right approach?

[@Udi-FPGA]

@@elfi2585 If you are generating data in the FPGA it will be much simpler to use AXIS bus (AXI Stream) it only has 5 signals data; valid, keep last & ready. Writing a data generator for AXI interface will be much more complex. After you have this data generator you can connect it to the S_AXIS_S2MM port in the DMA config the DMA like I did in the video and let the DMA store it in the Memory for you.
Another option is to use DataMover IP. This IP has a S_AXIS_S2MM port for a data generator with AXI stream bus (like the DMA) but it has a S_AXIS_S2MM_CMD port to give the command from hardware. It is very important that the data generator will send exactly the number of bytes the command wrote! If there is a different the Datamover will issue an Error which only reset can clear.
I think to make a video on data mover sometime soon.

[@elfi2585]

@@Udi-FPGA Thank you so much!