Simulation before synthesis is pre synthesis simulation. Simulation after synthesis is post synthesis simulation. Sometimes, synthesizing the RTL can change the functionality of the design. To check that does not happen post synthesis simulation is required.
sir please upload more videos on formality,we couldnt find any videos for formality anywhere.Please make debug session of formality as well.
In this if we got matched complete but have verification fail what to do then?
Good
Thanks Trupti.
sir, I have one doubt. In some books, its mentioned like pre synthesis simulation and post synthesis simulation. What does it mean?
Simulation before synthesis is pre synthesis simulation. Simulation after synthesis is post synthesis simulation. Sometimes, synthesizing the RTL can change the functionality of the design. To check that does not happen post synthesis simulation is required.