Getting Started with Verilog

[@mahaboobbashasyed7627]

brillant teaching

[@learningarabicwithjoy9061]

really helpful , thanks a lot

[@arafay142000]

Verilog HDL Complete Series | Lecture 3 - Part 1 | Data Types in Verilog HDL by FPGA made Easy. Subscribe to the channel "FPGA made Easy".

[@Deepak-ip1se]

Download the latest version of iverilog not the stable version if vcd file is not created by the command.

[@princessipsi9433]

It's Verilog or system Verilog

[@maradanitejaswi1201]

Verilog

[@arghya.7098]

he mentioned it is verilog, at the beginning of the course

[@Likith17]

You have this slides notes

[@thenortheasterwizard16]

indiano é foda! Tem tutorial para tudo

[@alterguy4327]

"Indian is F--ing has tutorial for everything" literally i had Google this

[@aayushsugandh4036]

When you dont know something, or dont understand it, please keep your mouth shut, idiot

[@shikharsrivastava8346]

@@alterguy4327 you are present here too!!

[@alterguy4327]

@@shikharsrivastava8346 We both have a common interest

[@aryanraj1765]

@@aayushsugandh4036 chutiya ho tum

[@mrpossible5696]

22.22

[@anuragsharma6471]

can we use modelsim

[@AbdulRazak-vb7vo]

Yes

[@arafay142000]

Verilog HDL Complete Series | Lecture 3 - Part 1 | Data Types in Verilog HDL by FPGA made Easy. Subscribe to the channel "FPGA made Easy".