( 15:56 )So when the 3 LUTs are used, the output of the 2 LUTs which are input for the 3rd one will have same level of delay that is '1' and whereas 4 LUTs part, ( 16:48 ) on the right side we have two LUTs and on the left we have one LUT so all these three are inputs of the 4th LUT which is on bottom of those, the left side LUTs take equal time/level to compute as compared to the right one. So the two LUTs on the left takes '2' delay level until that we get the output on the right LUT and the bottom LUT take one delay cycle so totally (2+1)~(2 delay levels on the left side + 1 delay level on the bottom)
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physical design- 3:05
various design styles- 5:25
which design style to use- 5:59
FPGA- 6:55
look up table 14:55
FPGA design flow 19:59
15:30
IM NOT UNDERSTANDING THE DELAY PART
Plz ask elaborately
( 15:56 )So when the 3 LUTs are used, the output of the 2 LUTs which are input for the 3rd one will have same level of delay that is '1' and whereas 4 LUTs part, ( 16:48 ) on the right side we have two LUTs and on the left we have one LUT so all these three are inputs of the 4th LUT which is on bottom of those, the left side LUTs take equal time/level to compute as compared to the right one. So the two LUTs on the left takes '2' delay level until that we get the output on the right LUT and the bottom LUT take one delay cycle so totally (2+1)~(2 delay levels on the left side + 1 delay level on the bottom)