14.2.3 DRAM

MIT 6.004 Computation Structures, Spring 2017
Instructor: Chris Terman
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14.2.3 DRAM
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[@omsingharjit]

1:55 what if instead of using single fet, we use tri state switch which can go high impudence ?

[@STRIKEcorperation]

Tri-state logic implies that the line is either pulled below a certain voltage, pulled above a certain voltage, or conducts 0 current. In reality, since memory is techincally analog, we have the option of conducting either a small amount of current or a large amount of current between the cell and the bit line. The FET is in "high impedance" when it is "turned off", but as Chris Terman mentioned in the video, the cells have to be refreshed due to both sub-threshold leakage and dielectric leakage. Even if the MOSFET was completely turned off, the cell would gradually lose charge to it's surroundings through the dielectric leakage.

[@lm645]

How much improvement would the proposed scheme be though you'd wager?

[@HUEHUEUHEPony]

gl simulating that