Thank you so much for this extremely clear, extremely helpful video series. I've recently started working in the DRAM industry as a designer and this video series is waaaaay better than any internal training materials that we have. I will be forwarding this video series to all fellow new hires from now on. Thank you so much again, everything makes so much more sense now!!!
I'm a minute late to the party, but THANK YOU for the series! Was trying to 'refresh my memory' on DRAM. had trouble finding content not too basic or complex, until I ran into this. So packed in value, especially for the time it takes to go through the series
There is some confusion I think, once you've activated a row, you can issue any amount of read bursts (n*bl8) to it since the row is still registered in the sense amps. Since there are quite a few columns you can do this quite a few times. Ofcourse you eventually will have to precharge/close the row due to refresh requirements and so forth. This way of doing things is sometimes referred to as open page policy.
This is the best explanation of DRAM Memory work on TH-cam. Is this LAST video for DRAM memory? Will there be something similar in the future for 3D NAND memory?
Thank you. I hope to add so much more to this topic one day. I am currently working on WiFi and Quantum Computers. I am a full time school teacher, which takes most of my time. I hope to retire soon and focus on this. In the meantime, please forgive my snail's pace of output. :)KD
Thanks... very structured and detailed. It would be nice to follow up with an example DDR IC and Controller interface(72bit ECC) pointing out the connection alternatives for multiple rank configuration.
Great set of videos. Is there a video already made to highlight the incremental innovation between different generation of DRAM technologies? Maybe take an example of DDR5 vs GDDR6
What I am asking myself: For a burst length of 4B, did it really make a difference to put the column MSB above the bank address? Because with a clean row-bank-column address map, if I am correct you would just read from a loaded row (open page) twice, before going to the next bank (meaning that still whenever you need a new row, you still access all the other banks first). Is it faster to access a loaded row in another bank, than to access the loaded row in the same bank twice in succession? (I could imagine it being like that, because a memory controller might use the peripheral electronics in successive banks in parallel, or even do lookahead)
Great job. A really fine series. Well organized. Well delivered. I am glad you included memory address mapping. I have been looking unsuccessfully for good, clear coverage of the topics of your series and not found anything clear and comprehensive, and then I found your fine series. One question. When there are two or four independent memory controllers, do these tend also to be multiplexed in the physical address mapping low order bits, for maximum parallelism, or do they tend to be high order bits? I would also be interested in multiple ranks but most interested in multiple controller channels. (FYI, I am most interested in Intel Core i7 Skylake and MacOS.) Thank you for a great series. (FYI, I would also be interested in a series on modern multilevel caches but only if it included explaining non-inclusive caches and cases where the memory controller can write to the L2 or L1 cache without writing the L3 cache (non-inclusive), and also whether writing a cache line back to main memory always writes all the bytes or can selectively write only the needful dirty bytes. I also have questions about flushing cache in a hyperthreading case when one of the threads gets swapped out.)
Can you make a video on refreshing the DRAM or refresh rate of DRAM. How are multiple chips refreshed in memory? Are they simultaneously refreshed as a whole chip or a whole row of a single chip is refreshed and so on? or is there already a video from you which covers this? Also I can't thank you enough for this amazing videos. Keep up the good work.
Hi Naeem. This is the final video of 7 in a playlist about DRAM. I may have answered some of your questions in the other videos. Please search my playlists for DRAM. :)KD
Each chip has its own chip select line so you really don't have to refresh all at the same time, however these chips are usually organized into groups called "ranks", for ex 8 (x8) chips would give you 64 bits of data for every query, since they function to give a full word it's not ideal to refresh only one chip but the whole rank together, if you have multiple ranks that can be used alternatively then yes you would refresh them individually while the other one would be used in the meantime. Also, dram requires all the cells to be refreshed in 64ms, however most drams can only refresh one/two rows at a time. Once you issue a refresh command the internal row counter is incremented by 1 and the current row is considered refresh. Issuing a refresh command once every 7.8us will result in 8K row dram to be fully refreshed in 64ms. The row counter returning back to 0 by the end of it. Chips with 16K rows will refresh two rows at a time so the idea is still the same.
I have one question: in the video, burst mode is used, to read multiple collums from one row. But i have also heard of "prefetch", which basically also allows you to read multiple collums from one row at the same time (DDR4 has a prefetch of 8bit, DDR5 one of 16bit). Is this type of prefetching (i am aware, this word refers to many other techinques) a synonym for burst mode, or can they be paired?
Thank you so much . I am really like your explanation . Is it possible to add some more topic in DRAM 1. Bank State Machines and Commands and wave forms 2. ZQ Calibration and training 3. On-Tie Termination 4. Jedec Initialisation 5. Error Handling
Great video series. Very illustrative. But I think there is a mistake about interleaving at th-cam.com/video/-xtWsQvOcjo/w-d-xo.html (and before). You say 8 banks are used to make a 8 burst possible. It seems incorrect, since most modern memory still obeys tFAW=4, which means for a same rank a max of 4 banks can be simultaneously opened. Therefore, the interleaving you explain does not match with the numbers. IMHO, when a column is read, it is already contain all data, and the column itself is divided and emitted in bursts.
Thank you so much for this extremely clear, extremely helpful video series. I've recently started working in the DRAM industry as a designer and this video series is waaaaay better than any internal training materials that we have. I will be forwarding this video series to all fellow new hires from now on. Thank you so much again, everything makes so much more sense now!!!
That's really great to hear. I'm delighted to be of service. Thanks for the comment.
Great Video Series.... Never seen such Graphical Representations which explain to minute details with Crystal Clear Clarity.
Thank you :)KD
The perfect videos for understanding DRAM. Thank you so much providing this high quality videos!!!
You are very welcome :)KD
Great DRAM Video Series. It's quite clear and very helpful to understand the main DRAM fundamentals.
Thank you :)KD
I'm a minute late to the party, but THANK YOU for the series! Was trying to 'refresh my memory' on DRAM. had trouble finding content not too basic or complex, until I ran into this. So packed in value, especially for the time it takes to go through the series
You are very welcome :)KD
All loud and clear, the essence all learning materials shall have but don't. Thank you so much
You're very welcome :)KD
Brilliant introduction to the inner mechanism of DRAM! Thank you!
Thank you :)KD
Great series !! best in youtube for DRAM !!!
Thank you :)KD
This was very much insighful , I'm thankful that it exists.
You are very welcome. :)KD
I design high speed boards for orbital spacecraft and aircraft, many DDR4 designs. This is an excellent series.
Thank you so much for this comment. It's great to hear from an aerospace practitioner. :)KD
Amazing video with clear explanation on DRAM...Please post more on DRAM series
Thank you. I will return to this series one day. I want to cover SRAM, flash drives and some of the newer technologies.
You are doing a really great job.
Good to hear. Thank you :)KD
There is some confusion I think, once you've activated a row, you can issue any amount of read bursts (n*bl8) to it since the row is still registered in the sense amps. Since there are quite a few columns you can do this quite a few times. Ofcourse you eventually will have to precharge/close the row due to refresh requirements and so forth.
This way of doing things is sometimes referred to as open page policy.
That's one elegant solution there.
agreed :)KD
one more video about "dram memory controller" and this series will be perfect .
I'll get onto it :)KD
Thanks for this beautiful series on DRAM's😍😍
You are most welcome :)KD
This is the best explanation of DRAM Memory work on TH-cam. Is this LAST video for DRAM memory? Will there be something similar in the future for 3D NAND memory?
Thank you. I hope to add so much more to this topic one day. I am currently working on WiFi and Quantum Computers. I am a full time school teacher, which takes most of my time. I hope to retire soon and focus on this. In the meantime, please forgive my snail's pace of output. :)KD
Thanks... very structured and detailed. It would be nice to follow up with an example DDR IC and Controller interface(72bit ECC) pointing out the connection alternatives for multiple rank configuration.
Yeah
Share if you found any :)
Super cool animations and explanation.
Thank you :)KD
thanks for this lecture, so clear and easy to understand
You're welcome :)KD
Thanks for your great videos. Would you please suggest to me some books title to comprehensively learn this topic?
Great set of videos. Is there a video already made to highlight the incremental innovation between different generation of DRAM technologies? Maybe take an example of DDR5 vs GDDR6
Thank you. I hope to add more to the series, one day. :)KD
What I am asking myself: For a burst length of 4B, did it really make a difference to put the column MSB above the bank address? Because with a clean row-bank-column address map, if I am correct you would just read from a loaded row (open page) twice, before going to the next bank (meaning that still whenever you need a new row, you still access all the other banks first). Is it faster to access a loaded row in another bank, than to access the loaded row in the same bank twice in succession? (I could imagine it being like that, because a memory controller might use the peripheral electronics in successive banks in parallel, or even do lookahead)
oh my word,this is amazing
Thank you :)KD
Great job. A really fine series. Well organized. Well delivered. I am glad you included memory address mapping. I have been looking unsuccessfully for good, clear coverage of the topics of your series and not found anything clear and comprehensive, and then I found your fine series. One question. When there are two or four independent memory controllers, do these tend also to be multiplexed in the physical address mapping low order bits, for maximum parallelism, or do they tend to be high order bits? I would also be interested in multiple ranks but most interested in multiple controller channels. (FYI, I am most interested in Intel Core i7 Skylake and MacOS.) Thank you for a great series. (FYI, I would also be interested in a series on modern multilevel caches but only if it included explaining non-inclusive caches and cases where the memory controller can write to the L2 or L1 cache without writing the L3 cache (non-inclusive), and also whether writing a cache line back to main memory always writes all the bytes or can selectively write only the needful dirty bytes. I also have questions about flushing cache in a hyperthreading case when one of the threads gets swapped out.)
Great video! May I ask how is having 9 bits possible? Aren't systems usually 4, 8, 16, 32 or 64 bit architecture?
Excellent videos, thank you so much!
You're most welcome :)KD
So detailed information
Fantastic!
Can you make a video on refreshing the DRAM or refresh rate of DRAM. How are multiple chips refreshed in memory? Are they simultaneously refreshed as a whole chip or a whole row of a single chip is refreshed and so on? or is there already a video from you which covers this? Also I can't thank you enough for this amazing videos. Keep up the good work.
Hi Naeem. This is the final video of 7 in a playlist about DRAM. I may have answered some of your questions in the other videos. Please search my playlists for DRAM. :)KD
Each chip has its own chip select line so you really don't have to refresh all at the same time, however these chips are usually organized into groups called "ranks", for ex 8 (x8) chips would give you 64 bits of data for every query, since they function to give a full word it's not ideal to refresh only one chip but the whole rank together, if you have multiple ranks that can be used alternatively then yes you would refresh them individually while the other one would be used in the meantime.
Also, dram requires all the cells to be refreshed in 64ms, however most drams can only refresh one/two rows at a time. Once you issue a refresh command the internal row counter is incremented by 1 and the current row is considered refresh. Issuing a refresh command once every 7.8us will result in 8K row dram to be fully refreshed in 64ms. The row counter returning back to 0 by the end of it. Chips with 16K rows will refresh two rows at a time so the idea is still the same.
I have one question: in the video, burst mode is used, to read multiple collums from one row. But i have also heard of "prefetch", which basically also allows you to read multiple collums from one row at the same time (DDR4 has a prefetch of 8bit, DDR5 one of 16bit). Is this type of prefetching (i am aware, this word refers to many other techinques) a synonym for burst mode, or can they be paired?
That was covered in the previous video in the series.
Thank you so much . I am really like your explanation . Is it possible to add some more topic in DRAM
1. Bank State Machines and Commands and wave forms
2. ZQ Calibration and training
3. On-Tie Termination
4. Jedec Initialisation
5. Error Handling
why don't we take the burst from multiple banks in multiple chips parallelly?
Very nice video! Can you help demonstrate on how BL=16, 16DQ works on a Die with 16 banks?
伟大！！！！
:)KD
Let's see if this helps me expand the RAM of my raspberry pi pico using an old SDRAM module I found in a drawer.
Sir, Nice lectures. Please try to cover LPDDR5 in your next videos.
Good idea. I've been thinking about a series on mobile technologies. :)KD
Any plans to cover HBM as well? Would be interested in HBM 4 @@ComputerScienceLessons
can you explain about mode registers
I plan to cover flash memory one day and will touch on mode registers when I do. :)KD
Can you please do a video on BNF and syntax diagrams? I have my A levels soon and I am struggling to understand them.
I will try to do something on these as soon as possible. BNF and syntax diagrams were dropped by OCR. Which exam board's course are you following?
@@ComputerScienceLessons Thank you very much! I am doing CIE 9608
Can you demostrate the use of singleton in vb.net(oop)
Singleton is easy, just a class can not more than one object instance, just point to one method
Great video series. Very illustrative.
But I think there is a mistake about interleaving at th-cam.com/video/-xtWsQvOcjo/w-d-xo.html (and before). You say 8 banks are used to make a 8 burst possible. It seems incorrect, since most modern memory still obeys tFAW=4, which means for a same rank a max of 4 banks can be simultaneously opened. Therefore, the interleaving you explain does not match with the numbers.
IMHO, when a column is read, it is already contain all data, and the column itself is divided and emitted in bursts.
if you are not the memory of GOD, then idk who is.
sorry, I mean the GOD of memories ;)