Time stamps for the different topics covered in the video. 0:52 SRAM vs DRAM 2:54 Dynamic RAM (DRAM) 3:56 Read and Write Operations on DRAM 7:15 Static RAM (SRAM) 9:22 Read and Write Operations on SRAM
During write operation, when we apply 1 to the output of a previously zeroed inverter, in the instant before its transition it will short the input voltage to ground, so for some pico second, the current will be very high upto a few Amps!! So, it will load the power line and will shut off the whole operation for a picosecond!!! Please explain it to me.
A. Research the meaning of the word pedantic. B. The traces on the PCB will have resistance, inductance, and capacitance which prevent an instantaneous transition to infinite current. C. The source voltage has a limit of current it can source. D. This is a super simplified diagram of the circuit. Obviously there are going to be current limiting resistors in any circuit. Don't act dumb.
What I meant to say was, using (4T) cell, we can reduce number of transistors (instead of bit) that is required for storing 1 bit of information. I hope, it will clear your doubt.
very easy to understand because you have used simple language and and a perfect reason behind why we use this memory. thank you so much. I believe you will further make many videos related to topic also like electronics devices and embedded systems also.
I still don't understand how that flip-flop loop in SRAM maintains the voltage without needing a refresh. I know there is no capacitor so you don't have to worry about a capacitor discharging. However, if you're not performing any operations on that memory cell for a long time, how does that voltage not fade?
OOPS, never mind. I just looked at the diagram again where you show all 6 transistors instead of showing each pair as a not gate. I can see that it's connected to VDD. So EVERY bit has a constant connection to power. That would also explain how an SRAM cell can turn a 0 into a 1. I'll leave both of these comments here in case someone else thinks the way I just did after seeing the video.
What I mean to say is instead of measuring the absolute value of the voltage, just by measuring the incremental voltage (increase or decrease in the voltage at the bit line) the reading speed can be increased further, as now no need to wait till the voltage at the bit line reaches the final value. I hope it will clear your doubt.
Emilio Ortega by density he means the amount of data it can hold for example a typical ram sticks nowadays can hold 8GB of data where’s the cache memory in typical CPU’s is very low like around 6MB of data
@@oliverenede7839 Hi thanks for answering, now it makes sense because he in the video talked about the number of memory cells and said Sram had less than DRAM :s and that's what I don't understand
There are different playlist on the channel . You can refer them. For example, for MOSFET there is a separate playlist. You can refer that for more info.
If you know about Flip Flop Or Latch then you can understand with the help of Transistors (1/2/3/4) we are trying to make a memory cell that can maintain a state as we do in FF/Latch. And voltage level we are getting as per the state of these transistor either High(say 5V) or Low (say 0V). These voltage levels depends on the source voltages (VDD/GND). HTH
I was wondering this! maybe there's a mosfet connected to the capacitor with an AC signal at the gate? if you used the clock cycle of the computer with a phase, I bet you could get it to charge only when there are no reads or writes occurring. really not sure though!
How they refreshing the capacitor periodically. And also my doubt is during the refreshing cycle the capacitor can become logic 1 suppose the data was logic 0. Please explain
Suggestion: Don't pause and raise your voice after every 3rd word. Example: The data [...] will be available at the? Data. (4:17) This is very disruptive. Other than that, well made graphics. PS: Maybe try to be pricise and don't say so many things multiple times
Hi, in an array of SRAM cell, can a specific celle be selected and written to ? It seems that the Word Line enable an entire Row of cell so we have to write and read to the entire row, is it correct ?
Sharon Alexander Not really. "Precharged" means that the data line WAS being continuously driven to be at 1V but now, it IS not. And it has remained at 1V simply because it hasn't been given any reason to change(it's like 1V was being supplied and suddenly, the voltage source was disconnected). The line is now free to take any voltage that tries to drive it. So, during the read operation, the capacitor will drive the line. However, during the write operation, the data line isn't "precharged" but is continuously driven from some source. Then, the capacitor will be one being driven.
Hi Vikash, Here transistors are used to get a latch of invertors(Latch/FF are used as storage element). And If you see at 7:35 you can see BL (Bit Lines) are controlling only Gates for these CMOS-Invertors and also connected to Output in READ mode. And voltage sources VDD and GND are present. Let say output of first and second invertors are INV-12, INV-34. So INV-12 is controlling gate of Second invertor. INV-34 is controlling gate of First invertor. Now consider that you want to WRITE '1' in this CELL. So BL == 1, and BL(BAR) == 0. It means INV-12 == 1: transistor 3 == open circuit transistor 4 == close circuit Output of second invertor is '0' that is matching with supported voltage of BL(BAR)
INV-34 == 0: transistor 1 == close circuit transistor 2 == open circuit Output of first invertor is '1' that is matching with supported voltage of BL And all these operation takes place only when WL make close circuits for 5 and 6 . So in absence of WL there is no change in gate conditions so no change in invertor conditions too. And output voltage controlled by VDD and GND and depending on current conditions of 1,2,3,4, transistors. In READ mode: we don't apply EXTREAM voltage on BLs, we just apply adequate voltage to check direction of resultant(of BL and Output voltage of invertor) voltage flow to decide Logic '0' or '1'.
since intel/amd days are numbering...in your future time, you might add the relation ship between arm and dram or sram or both...regardless have a great day and DO ENJOY LIFE !!!
Time stamps for the different topics covered in the video.
0:52 SRAM vs DRAM
2:54 Dynamic RAM (DRAM)
3:56 Read and Write Operations on DRAM
7:15 Static RAM (SRAM)
9:22 Read and Write Operations on SRAM
One video for the manufacture of flip flop 💾 pls....
Kash tum hindi mein explain karte then it will be more clear
"SRAM (Cache) is going to die out in the future." Ha ha amd 9800x3d go brbrbrbrbr.
This is the best lecture on DRAMs and SRAMs I've ever seen.
Instead of just explaining concepts like any other channel,you tried to look into common doubts and explained them.That's nice
Cant agree more
wow my English skill is very poor but I can understand this lecture cause you uploaded subtitles...! thx for great lecture and kind subtitle !
thanks a lot bro...
again thks for English...
many Indian education channels r in Hindi...
I think it's every usefull for non-hindi learners
THANKS WHE ARE DEPRESSED NON HINDI LEARNS CONTINUOE LIKE THAT
Easier to understand than my textbook, thank you sir!
Better than my teacher ever could teach
A very well explained tutorial of SRAM and DRAM...I highly recommend.
someone SALUTE this guy... MOST PRODUCTIVE 14 min spent in life
The best detail explanation of how SRAM and DRAM works i have come across Thanks......
Sir ,hum to aapke deewane ban gaye...
Your channel is the best for me
Thanks
Excellent lecture! Use 0.9x speed + subtitles, will be amazing.
🙌 Very well explained, but still in doubt regarding the power consumption comparison
Great comparison between the...DRAM. And the...SRAM. Very interesting...stuff
Very good. In depth coverage and that too very quickly without much jargon.
the video is so well explained even i being in the first month of college could understand
Excellent lecture!!!!!
Thanks
During write operation, when we apply 1 to the output of a previously zeroed inverter, in the instant before its transition it will short the input voltage to ground, so for some pico second, the current will be very high upto a few Amps!! So, it will load the power line and will shut off the whole operation for a picosecond!!! Please explain it to me.
A. Research the meaning of the word pedantic.
B. The traces on the PCB will have resistance, inductance, and capacitance which prevent an instantaneous transition to infinite current.
C. The source voltage has a limit of current it can source.
D. This is a super simplified diagram of the circuit. Obviously there are going to be current limiting resistors in any circuit.
Don't act dumb.
Thank you sir🙏🙏.
Your videos are awesome bro... Well researched. Thanks and please keep on posting. I wish your channel grow to millions and billions.😘
I could not get the line 8:37. Can you please rephrase that.
Thanks for this amazing explanation. Keep up the good work.
What I meant to say was, using (4T) cell, we can reduce number of transistors (instead of bit) that is required for storing 1 bit of information. I hope, it will clear your doubt.
Great video! Very good and clear explanation! Thanks man!
Very well explained in a simple way.
Just wooowww....tmrw I'm having Computer Architecture Exam bro..wish me
All the best for the exam :)
Nice video and its very easy to understand due to simple language have used.
Thanks
thank you for all your videos! you rock dude!
Around 8:40 you said that by using 4 transistor we can reduce no. Of bits required to store the bits..I didn't understand this part. Can u explain?
Is probably none sense. And while I have to admit that there are many resistors on a lot of PCBs, there are none inside an IC.
great info bro, your accent is perfect.
Worth watching bro.... Thanks a lot
Very simple and best explanation.. 👌 loved it..!
amazing video actually explains stuff
A great explanation. Thank you very much for the knowledge.
The best explanation sir. Really it is very helpful. Thanq
A perfect explanation.
very easy to understand because you have used simple language and and a perfect reason behind why we use this memory.
thank you so much.
I believe you will further make many videos related to topic also like electronics devices and embedded systems also.
Bro u r great, ur explaination is super
Superb!!
Thanks for create this video,
very much needed information
thank you
Beautifully explained !!!
Perfect explanation 👌👌
Great explanation, thank you!
Nice explanation,
Suggestion: Mouse pointer is not visible clearly. :)
It's very nice lecture
Nice video...quite helpful
you are amazing..sir
I still don't understand how that flip-flop loop in SRAM maintains the voltage without needing a refresh. I know there is no capacitor so you don't have to worry about a capacitor discharging. However, if you're not performing any operations on that memory cell for a long time, how does that voltage not fade?
OOPS, never mind. I just looked at the diagram again where you show all 6 transistors instead of showing each pair as a not gate. I can see that it's connected to VDD. So EVERY bit has a constant connection to power. That would also explain how an SRAM cell can turn a 0 into a 1. I'll leave both of these comments here in case someone else thinks the way I just did after seeing the video.
But Sir, why we need two inverters in case of SRAM? I think one inverter will be enough...then why two?
I can't understand what u are saying at 6:00 . Can u please elaborate it how we are increasing the reading speed further?= 2nd method
What I mean to say is instead of measuring the absolute value of the voltage, just by measuring the incremental voltage (increase or decrease in the voltage at the bit line) the reading speed can be increased further, as now no need to wait till the voltage at the bit line reaches the final value.
I hope it will clear your doubt.
I got everything but I don't actually get what you mean by "density" when you talk about the rams
Emilio Ortega by density he means the amount of data it can hold for example a typical ram sticks nowadays can hold 8GB of data where’s the cache memory in typical CPU’s is very low like around 6MB of data
@@oliverenede7839 Hi thanks for answering, now it makes sense because he in the video talked about the number of memory cells and said Sram had less than DRAM :s and that's what I don't understand
thanks a very good tutorial for beginners ...
at 8:39 , you said 'we can reduce no. of bits' how bits?
What I meant was, we can reduce number of transistors. (4 transistors in comparison to 6 transistor)
very nicely explained...keep it up
Bro and explain about word size and capacity of memory
Thanks for explaining the sram and dram thank you so much
It is used for my education
Why is it that asian dudes have the best content about computers and stuff? Not trying to offend! It's just a little trend that i've noticed
Nice explanation 👌👍
Where can i learn circuit components like you mensloned in this video?
There are different playlist on the channel . You can refer them. For example, for MOSFET there is a separate playlist. You can refer that for more info.
@@ALLABOUTELECTRONICS Thank you so much
DRAM 2nd point i.e It is fast compared to the primary storage memory like HDDs but it slower compared to the SRAM. Is HDD primary storage device?
12:13 I did not understand the SRAM WRITE operation.
very clear , thanks !!!
Sir how is value being read from the SRAM if there are no capacitors to store the charge or no storing device to hold the voltage
If you know about Flip Flop Or Latch then you can understand with the help of Transistors (1/2/3/4) we are trying to make a memory cell that can maintain a state as we do in FF/Latch. And voltage level we are getting as per the state of these transistor either High(say 5V) or Low (say 0V). These voltage levels depends on the source voltages (VDD/GND). HTH
Thank you for the teaching, very useful to me (dummy)
How periodic refresh cycles done in Dram for the cap
I was wondering this! maybe there's a mosfet connected to the capacitor with an AC signal at the gate? if you used the clock cycle of the computer with a phase, I bet you could get it to charge only when there are no reads or writes occurring. really not sure though!
great sir
excellent and simple explanation sir.pls share 8085 microprocessor course by you sir
1.34 "Primary storage element like hard disk drive" isnt it secondary?
How they refreshing the capacitor periodically. And also my doubt is during the refreshing cycle the capacitor can become logic 1 suppose the data was logic 0. Please explain
It was perfect thank you
Suggestion: Don't pause and raise your voice after every 3rd word. Example: The data [...] will be available at the? Data. (4:17) This is very disruptive. Other than that, well made graphics.
PS: Maybe try to be pricise and don't say so many things multiple times
Cache memory ke andar kon sa semiconductor technicq use hota hai......mos ya transistor...??
Please batao
you did well man.
Hi, in an array of SRAM cell, can a specific celle be selected and written to ? It seems that the Word Line enable an entire Row of cell so we have to write and read to the entire row, is it correct ?
I think you read out a complete row. You write to one cell by applying high enough voltage over its bit lines.
Good Job.
Can I use dram +sdram dual channel?
super excited sir
Can you use SRAM and DRAM inside one PC in the same time?
I love this video thank you!!!
And ssd kon sa technology use karta hai dram ya sram ??
Batao please
Won't the precharged bit line write into the capacitor during the read operation of the capacitor containing no charge?
Sharon Alexander Not really. "Precharged" means that the data line WAS being continuously driven to be at 1V but now, it IS not. And it has remained at 1V simply because it hasn't been given any reason to change(it's like 1V was being supplied and suddenly, the voltage source was disconnected). The line is now free to take any voltage that tries to drive it. So, during the read operation, the capacitor will drive the line. However, during the write operation, the data line isn't "precharged" but is continuously driven from some source. Then, the capacitor will be one being driven.
Good video
Is the SRAM with 4Cells the PSRAM (pseudo static RAM)?
Nice explaination but how can a transistor pair store a voltage?
Hi Vikash, Here transistors are used to get a latch of invertors(Latch/FF are used as storage element).
And If you see at 7:35 you can see BL (Bit Lines) are controlling only Gates for these CMOS-Invertors and also connected to Output in READ mode.
And voltage sources VDD and GND are present.
Let say output of first and second invertors are INV-12, INV-34.
So INV-12 is controlling gate of Second invertor.
INV-34 is controlling gate of First invertor.
Now consider that you want to WRITE '1' in this CELL.
So BL == 1, and BL(BAR) == 0.
It means
INV-12 == 1:
transistor 3 == open circuit
transistor 4 == close circuit
Output of second invertor is '0' that is matching with supported voltage of BL(BAR)
INV-34 == 0:
transistor 1 == close circuit
transistor 2 == open circuit
Output of first invertor is '1' that is matching with supported voltage of BL
And all these operation takes place only when WL make close circuits for 5 and 6
.
So in absence of WL there is no change in gate conditions so no change in invertor conditions too.
And output voltage controlled by VDD and GND and depending on current conditions of 1,2,3,4, transistors.
In READ mode: we don't apply EXTREAM voltage on BLs, we just apply adequate voltage to check direction of resultant(of BL and Output voltage of invertor) voltage flow to decide Logic '0' or '1'.
Super bro ...pls explain impedance
I have already made a video on that.
Here is the link : th-cam.com/video/7jw2_x8dyQ8/w-d-xo.html
kya ye video Japanese me available hai....?
are BJTs used in making cache memory?
No, MOS transistors are used.
since intel/amd days are numbering...in your future time, you might add the relation ship between arm and dram or sram or both...regardless have a great day and DO ENJOY LIFE !!!
very nice video :)
Thank you man
I can not understand Cell Address. Are you help me or make a video?
Sir shall you make a video on intergreted and non intergreted motherboard plz sir
Nice explaination
Fantastic thanks
Very good video but little fast...
Thanks!
I'd like to learn how to add something to calculate memory probability
Are the registers in cpu a cache memory
Although registers and cache memory are in the CPU chip, they are different from the cache memory.
Thank you a lot！ Sir
Thank you bro
Amazing!
Thanks for the clear explanation, also thanks for the subtitle23333