IBM VTFET: Vertical Transistors of the Future
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- เผยแพร่เมื่อ 20 ก.ค. 2024
- IBM and Samsung just announced VTFET: Vertical Transport Field Effect Transistors. In this video I will first give a brief introduction over the recent transistor history, from planar FETs to FinFETs and RibbonFETs and then explain why a vertical approach to transistor design solves many of today limitations in semiconductor fabrication.
0:00 Intro
0:43 Overview of current transistors
2:21 VTFET vs FinFET
5:18 When will VTFETs become reality?
Follow me on Twitter: / highyieldyt
Sources:
IBM PR: research.ibm.com/blog/vtfet-s...
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ydvisual made a really cool video, rendering IBMs VTFETs. Check it out: th-cam.com/video/3YrQzlFh0rY/w-d-xo.html
Oh wow, only 500 views??? You're underrated heavily. Keep up the good work!
I try to explain it in simple terms because that’s the only way I understand it too 😅 Glad you like it!
I found this extremely useful as I want to invest in the transistors category. It’s hard to find technical information that is short and allows me to learn if a certain company has a competitive advantage. Thank you for the taking the time to explain.
I hope you invested in nvidia XD
This is the best explaination yet, well done and thank you.
Great source of information for CS student. I appreciate the material 👍
Fantastic video and explanation. I glad I gave your video a view - happy holidays!
Thank you for your nice words and happy holidays to you too!
Good video....better than most....active operation illustrations are valued.....
Don't forget that interconnect resistance limits clock rate now days too.
I learned a lot from this. Thank you very much. (first time here btw .. I'll be back)
Simple design innovations with large impacts are always my favorite! Just goes to show you that no matter how much we evolve around or on top of something, all it can take is that one thing, that was once certian to be turned sideways and then EVERYTHING changes.
If you hear about it, it seems really obvious. It’s those kind of inventions that are really surprising to me.
@@HighYield exactly! I have had those kinds moments throughout my life where I figure out how to do something completely out of the box, that works perfectly. Then all of a sudden I can't even conceive how I never thought of it before. Curiosity can be just as of a prolific catalyst as necessity, so I tend to go down the rabbit holes when I come across them. The desperation that comes with "necessity" can definitely help let you consider things you normally wouldn't, but so can just really wanting to know. At least with me. I wish it was easier for people to practice that without so much risk. We miss out on a lot of Innovation for fear of what failure can mean these days. Anyway sorry, I'm rambling. Thanks for the video!
@@HighYield To me as well. This whole time I thought that transistor gates where simply open or closed. I had no idea about this leakage, and it seems like an obvious problem that all chip manufacturers had to see coming down the road as being increasingly problematic as production (intentionally) size scaled smaller. Why they waited this long to address it is confusing.
@@THE-X-ForceThe transistor short channel leakage effect became a bigger issue around 2012, as video says. Things were done to minimize growth in leakage without radically changing the transistor design. The FINFET, GAAFET and VTFET are all a pretty large shift in the manufacturing process and it takes time to use the equipment and change the equipment to execute the 1000s of manufacturing steps in a high yield, low cost way.
"We need to blink twice and it will be a reality" as opposed to clicking our heels three time and saying 'there's no place like home'. 🤣 great video 👍
New Stuff. Thanks.
Hi, great video, but I was wondering what is the difference between a CFET and a VTFET?
Cool stuff. I wonder how these new transistors will compete with current technology in terms of price - wouldn't the manufacturing costs be higher given the increased complexity in production, even after optimizing production lines etc?
That being said, it's great to see things like this in development. It all seems like magic to me.
I#m sure costs will be higher at first, but when this really scales like IBM predicts it might be the only transistor used in the future. Just like right now everyone who wants to compete at the bleeding edge of tech uses FinFET.
thx bro~!
If you didn't post this video, I will reiceive the grade F
Glad my video was helpful!
Can you do a video explaining the new breakthrough in Adaptive transistor 85% germanium efficiency?
I read about it, as far as I can tell its a lot more theoretical that VTFETs right now. But maybe I'll do a video in the future, lets see how it develops. The base idea seems to be a transistor that can switch how it functions.
Transistor design always evolve. And yes, means better performance and efficiency for Most Computing devices
FinFET has been the standard for quiet a while now, lets see how long it takes for VTFET to take its spot.
Hey High Yield! Great info thank you! What I don't understand is the single vtfet diagram by IBM has one drain, one source and one gate(blue color). But in the the larger image with many many vtfets together in rows, the gate(blue color) is in the middle between TWO drains and TWO sources... Why is that? and sometimes there is no gate(blue tall thing)...
I'm not entirely sure, I think is either a visual error or maybe trying to show that you can increase the size of source/drain?
@@HighYield Hello again! Thanks for replying! Actually, since the day I saw your video I have been studying the VTFET (and FETs in general). I think what we see in that IBM image are CMOS transistor pairs. In most logic circuits there are PMOS and NMOS FET pairs (CMOS = PMOS + NMOS) which share one gate (the blue part). I will try to make a good animation of how I think this works and show you!
@@ydvisual5530Yes, the gate connection represents a an input to a logic gate (NAND, NOR, AND, etc.) and each logic gate input is connected to a single PMOS transistor and a single NMOS transistor; always two in CMOS logic gates.
Each PMOS transistor is in the pull-up network for the logic gate output and each NMOS transistor is in the pull-down network. The number of transistors and their organization into series or parallel connections creates the difference between the Boolean logic gates and the number of inputs to it.
I’m really worried about interconnect limitations for this
Mhm. How does vtfet help reduce gate capacity, if everything is larger? Isn't this necessary to help reduce switching power consumption to harvest efficiency gains from the upcoming processes? Or you say with every shrink, leakage current becomes larger, so how did newer semiconductor nodes become more power efficient so far over time?
I wonder if they're planning to make vtfets as complimentary pairs stacked on top of each other as well for better space efficiency... or even eventually a fully vertical universal gate?
I should say the video wluld have been more comfortable with more Broll from the infographic animations. In a pinch, just pause on the broll or loop it or both to give us more time to inspect it. Not fatally so but you know quality of life features.
Yes, it would be ideal to have the source, drain and gate areas and capacitances shrink. That’s what happened with Dennard scaling of planar transistors for so long, in the past.
But even if the gate, source, drain capacitances don’t go down, the interconnect can become shorter with increased density of transistors. Both are contributors.
The leakage current is a non-ideal static, off-state current that increased and only became significant as transistors became too small. The power required to switch the capacitance of the wires and connected sources/drains/gates/outputs is the 2nd, and ideally more dominant, component of total power consumption.
Before ~2010 leakage power was not significant. FINFET, GAAFET, VTFETT all address leakage by ditching the planar transistor. But there were process tweaks before that that made a little difference, without such huge changes to non-planar designs.
... well the first thing I notice, is it's CLEARLY going to take up less space. That's going to result in a BIG jump in transistor density.
Improvements in speed or efficiency are like Ford of General Motors telling you about higher power, or higher mileage. That's great, but what the car company cares about is margin and profit and cost of manufacture. You increase transistor density and that's money in Intel's pocket.
Increase in density and electrical properties at the same time seems like a jack of all trades. I really hope it will become reality in the near future.
What is the difference between GAAFET and VTFET?
VT-FET describes the vertical alignment of transistors and is still in early development.
GAA-FET is a traditional horizontal layout, but the gate wraps all around source-drain interconnect, and thus has more control over the flow of electrons.
Anandtech has a good article about Gate-All-Around: www.anandtech.com/show/17474/samsung-starts-3nm-production-the-gaafet-era-begins
@@HighYield I think the GAAFET is an evolution of FinFET.
Yes, you are right. GAAFET is the next step after FinFET.
@High Yield I think Samsung and IBM are completely building VTFET from scratch. There is no correlation between GAAFET and VTFET.
you are too young to remember this, back in 1980's, there was the permeable base transistor, in which transport was vertical, though different than this. The first(?) wafer showed outstanding performance characteristics. Everyone was really excited. But every subsequent attempt to produce new wafers were nowhere close to the original. they kept doing research on devices from that first wafer. and eventually gave up?
A lot of tech, especially in semiconductors, literally takes decades to mature and come to market. Its really interesting how "old" ideas dont come to fruition, but then 30 years later they appear again with some slight tweaks.
So in the future, CPUs will look like highrise Big Mac.
If this comes to market, yes, they will look like Manhattan. But I dig it!
they are working with ATOMERA MST