Steam Deck Chip Deep-Dive (Van Gogh/Aerith)
ฝัง
- เผยแพร่เมื่อ 7 ส.ค. 2024
- A deep-dive into Valve's Steam Deck Aerith APU / AMD's Van Gogh with never before seen die-shots from Fritzchens Fritz.
Fritzchens Fritz
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0:00 Intro
1:00 Van Gogh die-shots & specs
2:09 LPDDR5 PHY, Memory Controller, VCN
3:14 Zen 2 CPU cluster
6:26 RDNA2 GPU
9:10 I/O, USB, PCI-E
10:59 The Secret
11:40 Magic Leap 2 Mero
12:23 14-core CVIP
14:01 6nm Steam Deck OLED shrink
16:31 Final Thoughts - วิทยาศาสตร์และเทคโนโลยี
AMD's CPL acronym is actually 'Chip Pervasive Logic'
That's interesting, so it doesn't have anything to do with the current privilege level at all? What function does the CPL have?
@@HighYield thread security and privileged-ness is built into lots of different units all having to do their part to keep the entire system secure.
CPL logic includes things like clocking, test, and voltage domain crossing structures that are used all over place.
I find it insane how tiny the area of the combined CPU and GPU take from the whole die.
This is why it seems surprising when some claim: "Apple's CPUs are *only* fast because Apple has huge die space to spare. Apple doesn't sell to anyone else, so their CPUs can be really big without consequences. AMD & Intel could never do that!" On any modern SoC, the CPU total logic area is one of the smaller structures: I/O, GPU, NPU, caches (!), etc.
Yeah, espcially since the Steam Deck doesn't need a lot of that. A truly custom APU wth e.g. 4x Zen4c and 12CU RDNA3, 4x PCI-E and maye 2x USB could be even more compact. I'm really excited what Valve will cook up for the Steam Deck 2!
@@ikjadoonwhat would be interesting is how large Apples process-node advantage is. They sell less and more high-margin items than the others so it makes sense for them to be on the cutting edge. The others would likely not even be able to get enough production volume from TSMC.
Anyway, I would like to now how much of their performance improvement is due to technology, not necessarily architecture.
Personally I think it is doubtful that on these large performance oriented designs the difference is due to ISA. Its likely technology and other architectural choices. (At some point all ISAs start being micro-instructions anyway so you can decode and execute them in a more optimized fashion.
@@PhilfreezeCH look at the performance changes with the iPhone 13, 14, 15. N3 was not ready for the 14. The this year only the 15 pro has a chip using N3.
@@HighYield Will also be interesting to see what they cook up for the Deckard, since there are rumors its going to have some sort of x86 APU.
It's incredible how little area in the CPU core is actually dedicated to arithmetic, as opposed to cache, scheduling, and memory management
no point in adding arithmetic units to CPU, if you can't feed them, branch/cache/memory prediction is the most important part of CPUs nowadays, branch predictor was the biggest block on main core area 4:59 not including l2 or l3.
The cores in these chips are cut down zen 2 cores, especially compared to the cores in a traditional desktop zen 2 cpu.
@@BGTech1 they are the same zen 2 cores, nothing is cut down except l3 cache.
I like to think of modern CPUs as fast instruction processors that just happens to do compute. If you need high compute performance, there's probably dedicated hardware for that. But those sacrifice fast instruction processing for compute.
CPU design is weird. It's mostly written in some HDL (some by hand EE stuff) of the designer's choice, and you can transpile C to it totally fine. Any code written in it is executed as close as possible to instantly as a physical structure on some sub-section of the die. A lot of those management things are just huge pieces of logic that would take too much time or energy to compute iteratively (think 1 cycle for like 100 gates ish equivalent, excluding latency things) and a lot of them are predictive to try to avoid latency. It is quite common now days to take an AI Model, convert it to HDL and some bin files, and just throw a whole projective knowledge model in there that's been pruned to usually like some int datatype and with significantly smaller layer dimensions.
I don't even want to get into what microcode is or OOE but man, there's like a whole crappy 'OS' made out of transistors around every processor block for like the past 30 years or so. That 'OS' could be offloaded some to drivers if it is too complicated or space/energy/latency consuming, but it's usually too single use to really be considerable. There's also the PSP on this die and who knows? Sometimes there is essentially bloatware on your die from the tier 0 OEM, it's annoying and crazy. The reason I say that 'OS' is crappy is also literally every hardware bug ever that's not based around firmware.
Source: Me, I design CPUs.
@9:40
I've been working with PCIe at low (near-chip) level a bit, and it is much, much more, than just the PHYs.
This is more akin to Ethernet-like packet switching network, and the controller needs to be able to replay any buffer (data), that was lost or corrupted in transmission.
These replay buffers can actually be quite large (even in terms of megabytes), since the PCIe controller has to keep data in them, until it receives acknowledgement, that it arrived to destination device intact. So buffers need to be large enough to keep all the possibly in-flight data, in order not to block the transmission.
Also, the controller has to (de)serialize data into/from packets called TLPs, and sometimes, include quite complicated logic to ensure good performance, fairness of data transfers and so on. And I haven't even touched on IOMMU - the PCIe endpoints (devices) can actually initiate reads/writes to memory, and we may need to ensure, that these addresses are translated correctly, and that R/W permissions are OK.
Summarizing, large logic structures with SRAM blocks can be the PCIe controller.
As a chip engineer I always love seeing these die shots and breakdowns. For me it's a lot of lines of HDL and papers to sign off on, and then I move on to the next revision or next product when results come back from the fabs. MTL is the most recent thing I helped with to launch, and the next for me is LNL. I'm not an architect for CPUs or GPUs, I just glue chips together and wire up busses.
From what I can see in the shots from Fritzchens Fritz, I think you're correct about the central section of those 14 cores being some kind of bus. If you look very closely you can see higher density (noisier) sections periodically near each core. I suspect the area above the main 6 cores to the left of the smaller 6 is some sort of interface block to get to the rest of the system, as it also appears to have a couple of stops on it. That would be 16 stops on a ring bus, which is a lot, but not too many for something like a VPU or NPU that doesn't need super tight core-to-core latency specs.
The CVIP area has other implications aswell: Valve is currently working on their Deckard VR system, which will replace the current Index. According to leaks Deckard will feature a ARM and X86 APU in some form. The index used FPGA to enable the usage of the Lighthouse tracking system; if they want to get rid of that to reduce costs, a APU that can process visual data fast (to enable camera based tracking) should help here.
Hey, as someone who has been doing chip annotations for a while (under the GPUsAreMagic name, mainly on twitter), I salute you for this deep-dive, the layout and analysis are spot on as far as I'm concerned. And the juicy find of the CV cores is quite exciting!
A few things to address which you brought up throughout the video:
The GPU "Misc" area can probably be labelled if you trust some of my RDNA2 annotations, but due to this being a single shader engine GPU, it will still be very hard to distinguish the SE, SA and command processor as there will just be a single one of each.
Your hunch for the display PHYs being above the PCIe PHYs is probably correct judging by other AMD chip pics, which means VanGogh has 2 dedicated display PHYs.
The USB port spam is quite surprising, but keep in mind the 2.0 PHY is physically separate from the 3.2 PHYs (since the data lanes are also separate, a 3.2 cable still contains the dedicated 2.0 signaling), which means (judging by older chip pics) the two thin PHYs under the PCIe area are likely just straight 3.2 PHYs, the slightly bulkier ones below that probably support DisplayPort Alt-Mode.
CV cores I sadly don't have anything new to add as I'm absolutely clueless with how those could possibly look like, but the general slicing and guess-labeling you did seems pretty accurate. It also bears quite a big resemblance to other "relatively simple compute but spam a lot of it for AI/CV" engines such as Apple's NPU.
Fritzchens Fritz uploaded the high res images on his Flickr, maybe you can find/label more areas. The originals pics are super detailed.
@@HighYield You can be sure I will take a look at it when I have some time :D
I've been waiting AGES for a proper high-res die shot from Fritz, and you've given a great analysis of the chip to go along with it! Pierre-Loup Graffais confirmed to me around the announcement of the Deck OLED that part of the size reduction came from removal of some unused components, which had to be the DSPs, so Sephiroth should look pretty close to N7 VGH outside of that.
He will release the Van Gogh die-shots very soon. The initial plan was on the same day as the video, but due to the holidays he needs a couple more days for the upload. They are coming in crazy high detail, much more than a 1080p YT video could show.
subtracting the DSPs' 22.2mm² gives 143.85mm², which would mean an ~8% shrink to get 132.65mm². Much more reasonable!
Looking at Van Gogh makes me think just how versatile Zen 2 was for AMD. They had it for desktop, mobile (Renoir), PS5/XboxSeriesX/S, and will have it for Mendocino in both TSMCs N7, N6 flavours and I think each iteration has slight changes in design as well. I'd really like to see an N6 shrink of Zen 2, maybe someone has a broken Oberon Plus as well?
The Steam Deck OLED has the Zen 2 cores in a N6 shrink already, and it's very efficient.
@@aviatedviewssound4798 Yup, added the revised PS5 as well so we don't need to just donate a broken Deck OLED as well lol. Also this just came to mind, but I wonder how similar Mendocino with 4 Zen 2 cores and RDNA2 w/ 2CUs is to the OLED SOC? OLED is around 132mm^2 while Mendocino is about 100mm^2
@@NootNoot. The Zen 2 cores are actually more efficient in terms of design than the Zen 3 cores, but the Zen 4C is shaping up to bring back that Zen 2 efficiency. The fact that the die is still bigger might be a fact that they've just reduced the number of AI cores but still kept them for future AI workloads in gaming.
Zen 2 was AMD's breakthrough. Small, efficient and fast.
Ps5 Pro's rumored to be on zen 2 N4 isn't it ?
In the LCD BIOS the CVIP cores are mentioned, for example you can change their voltage. It is definitely 'powered on' by default. You may be able to use ROCm to utilise them or amd openvx / mivisionx.
I’ll look into this on my LCD!
@@etzabo What did you find?
Cool discovery! It's almost like this could have been in a tablet, or something camera- centric. Steam AR?
It's also astonishing to think that it was easier to keep these parts not used in the Steam Deck than do a separate design. Shows how much effort/ expense each physical design is!
I think Steam/Valve are making a new AR/VR headset. The name 'Deckard' has been floating about. Although, I haven't caught up in the leaks or rumours, so idk if the SOC will be AMD, or even x86 based. Perhaps ARM?
There's a lot of product synergy for sure. If we could confirm that the CVIP cores aren't part of the 6nm APU, we can basically be sure that the Steam Deck is selling good enough to finance a re-design.
This is because aerith was originally for a microsoft surface tablet conputer
Something like a Microsoft product?
the die looks like a map view of a factorio megabase
If you zoom in, it looks like a 80s video game.
What I always find incredibly interesting with CPU designs is how much chaos there is. You get things like the cache blocks that look like lines and rows and then other spots that look almost organic in design.
I had no clue Van Gogh was used for something else that isn't the steam deck. very educational and amazing video
Hopefully Valve locked that silicon away with software instead of with physical modifications because it would be cool to “unlock” more capabilities on the older SteamDeck APUs.
You deserve more subscribers. The content is absolutely phenomenal and highly informative even with the Apple content you have made as well going over to the Apple silicon chips keep making these awesome deep dive rabbit hole silicon videos
Glad you enjoyed the video. And tbh, 30k subs are already a lot.
So you were cooking! Minutes in and I can tell production has ramped up! Top down view of a Steam Deck board, and a sweet b-roll intro of Van Gogh courtesy from Fritzchens Fritz (which I have finally learned the correct pronunciation of lol)
I was so hyped once Fritzchens Fritz was onboard, it felt illegal to be one of the first humans to see Van Gogh like this :P
Wow, I did not expect such a large AI processor sitting there disused for steam deck devices, huge find.
Is it possible we could see it activated in an update?
Ahh this may explain the massive area reduction. That was the first thing came to my mind when I saw the side-by-side die shot in the GN video. Thank you.
Great piece of content, thank you for making it! Cannot wait to see the SteamDeck Oled die shot breakdown and analysis!
Damn insanely cool find, I haven't seen anyone talk about this at all. A whole core package unused revealing interesting details about the business/design of the steam deck. And even without that still a interesting video to see what's beneath!
Ok, digging into the cvip we need to modify the acpi table in the bios and add an AMDI0068 entry, then we need the kernel drivers: mero_cvip_thermal.ko, amdgpu.ko, cvip.ko, cvip_s_intf.ko, cvcore_trace_kapi.ko, gsm.ko, mero_notifier.ko, mero_xpc.ko, mlnet.ko, shregion.ko
these are under gpl, yet not published. Does anyone wants to ask magicleap for the source code?
Holy cow cool find! Love die shots they're my fav, keep it the heck up
Great Work. Looking forward to the update with the input from the community.
Crazy high quality pictures and video analysis, love those!
This was amazingly interesting. Absolutely grateful I have notifications turned on for this channel. Happy holidays, High Yield!
One of my favorite videos that you've made. Felt like an mystery.
Loved this video! Well narrated and very informative.
We absolutely need a follow up of the 6nm refresh chip
this was a beautiful video! I hope you get to do more of them! Even if it's not something niche like a steam deck this is a delight.
Amazing video - hopefully it gains some traction and translates into some growth for your channel, you deserve it.
WOW! I am truly blown away. This was truly incredible to see. Thank you so much!!
Amazing video and great efforts, with @locuza no longer doing die shot labeling, it's hard to find such information, I've always wondered why steam deck APU die size feels larger than it should be, that CVIP core part was unexpected. Never thought of AMD into AR market. I hope you'll be able to continue this amazing work in future.
Amazing video! I love how it looks like satellite imagery when you really zoom in.
Thank you! 🙏Great work!!!
I don’t have to justify why I love this kind of videos 😁
You could maybe collab with Locuza for details on the layout of the die
Love this stuff bro keep it up!
incredible analysis. it seems to me that your hypotheses was spot on
Very interesting! Thanks for sharing this!
Thanks for this! Your speculation on the chips and Valve sharing the risk make a lot of sense. Looking forward to your OLED video...for science
I love these chip analysis vids
Super video, thank you very much. If possible please upload future videos which include die-shots in 4k so that we have a better quality image.
Fritzchens Fritz will upload the high-res die shots on his Flickr account. It's delayed by a few days due to the holidays.
Good stuff. There's room to speculate about Valve sharing a chip with an AR company while planning their own new XR system, which is assumed to share a lot of silicon with the Steam Deck.
damn i enjoyed this video so much!!! seriously your videos are just in another level ❤
amazing shots and great description of the components of the die, glad to have found this channel.
you know which die will be interested for a video? a damaged Xbox 360 GPU affected by the Core Digital Error (the infamous Red Ring of Death) since the damage was on the physical layer of the die due to low transition to glass of the underfill used on the early chips.
Amazing video thank you so much for sharing.
Thanks for watching!
Awesome video! I'd love to see more stuff like this if you can afford it
More to come for sure, my dream would be a $20k Nvidia H100 :D
I absolutely loved this walkthrough of the die
Thanks, that was very interesting!
Very cool video!
The motherboard at #0:17 is not a first generation LCD steam deck motherboard, 1st gen APU, sure, but more like third generation motherboard (if you count original dev unit, then release unit, and then the revised release unit before the OLED), the APU is rotated and the WiFi adapter is angled and not situated underneath where the SSD would reside, this isn't the case with the first gen LCD Steam Deck.
Great work. News outlets are going to talk about this.
Thansk, but I'm not sure this is news worthy :D
wow, you know so mcuh about this stuff! mad respect
I literally learn on the go.
great and interesting discovery!
I have never heard of the magic leap 2, interesting find!
Your magic leap theory is really interesting. We need someone to donate a 6nm sepheroth chip for dissection!
Great video as always, keep'em coming.... Watching this makes me really curious for Nintendo Switch 2 's SoC and Valve's own Steam Deck 2 SoC, hopefully with Zen 4 cores and more GPU compute units and smaller process node it would be a beast. And hopefully they don't put disabled cores in it intended for other devices, space is very precious.
I think the earliest valve will try for steam deck will be zen5 rdna4 if they both turn out to be really good
Otherwise most likely zen6 rdna4.5
Zen 4 and RDNA 3 APU's are already on the market with Asus ROG and Lenovo Legion Go, assuming a Deck 2 is released by 2025, I expect it to be at least Zen 4 but probably Zen 5, depending on release, maybe Zen 6 but I doubt Valve would want to wait that long, as for the gpu, It's very likely to be RDNA 4 or 4.5, depending on when the Deck 2 is released and AMD release it's new architecture changes for it's cpu's and gpu's.
All this is going on the assumption that that Valve will release a Deck 2 in 2025, which I think they might have too because other rivals like Lenovo and Asus could release their second hardware upgrades to their own portable devices, which if they do, the Deck would look quite dated and expensive if it doesn't get a big price drop by then.
Looking at what rivals are doing in the portable space already, 8 cores seem very likely for a Deck 2 and also needed for games going forward, but the gpu performance is hard to guess, it will probably be around double the performance of the current Deck, maybe more, but I suspect ray tracing performance will be a lot better and it will be able to do A.I. workloads, going beyond that performance level like other rivals will probably want to do will probably be too much for having decent battery life, which the Deck OLED is in a good place on that and I doubt most gamers will want to take a step back from that.
@@paul1979uk2000As you can see Steam Deck can already do "AI workloads" just fine, the problem is the software...
Cool video
This looks like a Factorio map of a megabase zoomed out
If you think about it, not a bad analogy.
Incredible
Excellent deep dive chip analysis also thx to high res pics from Fritzchens Fritz!👍AMD SoC was an obvious choice with much better efficiency in comparison to Intel offerings however, Arm based cores if optimized and more widely adopted in games would be even better choice for handheld like Steamdeck.
The only pc handheld to get a custom made apu just for that handheld
Well, I didn't watched full of Steam Deck Product Review but knowing chip inside of it is actually fascinating
Interesting Van Gogh is also used by AR headset, then it can also be used for new Steam VR headset.
Thanks!
Thank you, I'm glad you enjoyed the video :)
Interesting to see how little space is actually used for CPU and GPU on the die, completely differnt from a Raptor lake core where basically everything is CPU cores with a little bit of GPU on the right and a bit of IO on the left
7:35 that should have been "work groups" i assume
There are some old roadmap screenshots that mentions Van Gogh CVML bullet point
Do you know where I can find them?
Never saw You replied. Google Notebookcheck Van Gogh roadmap
I am really getting sick of YT not recommending or even notifying me of when your videos release. I even went through and turned off all notifications for all other subs and made sure yours was still set to "all". About ¼+ of my recommendations are brand new channels made via AI that are like a week old with 100 views or something to that effect. Is there anywhere else I could follow your work besides twitter(not calling it "X" because Im not a 7th grader or musk lol.
Anyway, regarding the context of the video, this is very interesting! Sometimes I feel like you are one of the few people that get as excited by APUs as I do lol.
Im interested in hearing your thoughts/knowledge on/about AMDs new desktop APUs. I am curious if they will bother releasing a RDNA2 APU for destop or just skip right to RDNA3? I know the PS pro will be getting a RDNA3 APU even though it still uses a Zen2 for compatibility. Since we havent got the ones in the original PS & XB, seems like they might as well. Also, do you think they will jump up past zen2 to like 3 or 4? It would be nice to have an APU that can use fast DDR5 since that would be much closer to VRAM than DDR4. I wpuld LOVE to see APU mobos that can have dedicated VRAM slots. If they did, soon, they could provide the console death blow we(PC gamers) need to get games that actually take advantage of a PCs capabilities other than graphics. Imo it seems that since like 2006 games have been deved for consoles and (POORLY) ported up to PC. Unfortunately it also seems that each console improvement per generation only improves the graphics wrapped around the same old capabilities. For example, PC games from 2005 have way better environmental and NPC "AI" than games that just released. That wouldnt be that bad if the PC version was better and ported down to console, but since you will not get a license for a console if the PC version it too much, if any better than the console. Hence the inversion from porting PC to console, to porting console to PC. I know I keep.saying all.of this, but it is a issue that gets to me....clearly lol.
Thanks again for the hard work and video!
YT doing YT things, tell me something new... :D
I've been a fan of the APU idea ever since AMD's slogan was still "The future is fusion". I've also heard the PS5 Pro rumors, but I don't fully understand why Zen 3 wouldn't be compatible. Especially since Zen2 still uses 4-core CCX, it would make sense to upgrade to Zen3. A 5nm re-design of Zen2 feels pretty strange to me. I have zero new info on the PS5 Pro, but if there's one, I would hope for Zen3 + RDNA3.
Most likely skip directly to RDNA3 judging by recent leaks.
CES is a few days away anyway.
@@HighYield I know that consoles like PS and XB use the hardware differently than a PC. That's the only way they can get the "performance" that they do considering. Their "OS"/"Kernels" may be designed specifically for a specific architecture either to get the power they want out of it, to allow the APU to use more of a VRAM instead of sharing DDR4/5 system RAM, or for "security"(anti-piracy). Idk, this is pure speculation, but there has to be some tweaks because I feel like they are able to get a lot more out of an APU on a console than a PC. Seemingly more than RDNA2 could over Vega11, but I could be wrong.
id love to see oled chip analysis, also what about top right side of this chip? what are those?
Today youtube algorithm is pretty cool - got another high-quality tech channel.
Insta-sub!
Any idea where the trustzone ARM core is on the die shot?
I just got a Steam deck. Lovely little thing! Very impressed with the sheer power of it and was worried it would replace my Switch. Alas after scorching a load of games to fill the 1tb storage (I have a 1gbps web connection) hooking it directly to the main router, I've had nothing but crashes galore and wasted too much time fiddling to get it working. Memories of wasting time on computers… working all day to fix my iPhoto or iTunes libraries. I don't get the appeal now of tinkering with unenjoyable stuff -- now -- tinkering with fun things like a recurve bow to get it in the gold on a target that's 80m away. Now that's fun :)
I just need an analysis of why, when I open the deck back into games sometimes, only rhe left audio channel works. That’s with Bluetooth and aux…
And now suddenly, the aux jack _always_ only has the left channel, and that’s with multiple headphones.
I’d use Bluetooth but the delay is far too much for gaming, even if I change the codec.
I suppose it’s possible the right channel of the aux broke somehow (while the Deck was sat safely in a drawer for a week since e the previous use), but I think something happened when I had the usual issue and went into desktop mode to see if anything weird was going on in the audio settings.
I’m on the verge of doing a factory reset
This design needs 4x zen4c cores, 4-6 GPU WGPs, and a real-time RISC area for sensors.
WOW!
great analysis!!
so whats with the unmarked die area in the top-right? 12:40
I'm sure there's a display engine somehwere, system management unit, and much more. Hard to tell exactly.
@gamersnexus needs to investigate
I think that Valve could have at least tried to do some AR/VR headset add-on that take adventage of that 14core CVIP engine, or they could have try to use it for some proprietary technology (real-time AI upscaling idk...)
With how little space is dedicated to arithmetic, it begs the question when OOO execution and a RISC backend will no longer be necessary and we will be able to make a native x64 1 instruction/clock core.
i find it funny that the physical shape of those tiny ram controllers to be similar to the full desktop ram shape 😂
Hmm, maybe there's a reason. I mean the PHY is used to provide the physical connection.
For me, the CPU, GPU and caches are less interesting to me. Its very interesting to see the the change in patterns as you zoom into the SERDES where you see a lot of hybrid analog digital circuitry.
this is what research looks like
And it was a lot of fun!
@@HighYield and yet more fun ahead! :)
So the Steam deck got quad channel memory while desktop AMD users have to make do with dual channel.
With all the talk about how Valve’s next headset potentially using Van Gogh and it being a standalone headset. With them removing the CVIP portion of the chip, wonder if Valve has decided to use another upcoming APU instead?
SadlyIsBradley has talked about this for the past year or so xP
I read that the AMD Zen contain also ARM class CPUs inside them, similar to those found in smartphones [...] perhaps you have identified precisely those units?
Wasn't that the security processor that AMD CPUs and APUs have?
The Platform Security Processor.
I told you Valve was hiding much more than you guys think. 😆
Kinda disappointed about the unused section being removed in 6nm. When i read the news i thought maybe this section would have a link to the "deckard", but this doesn't seem to be the case if they've scrapped it.
It’s just a theory until now, I’ll need to look at a 6nm chip to confirm. But yes, wouldn’t make sense to scrap it if they want to run Deckard on it.
Can I recommend you to more obviously mark what part of the APU you are talking about? As someone who often reads with subtitles you start talking about a part of the die, which makes me look up to see what part you are talking about. But I have trouble actually seeing which part you're talking about even if you marked it with text. I think either using simple arrows or flashing the text for a few seconds could help a lot!
I'll keep that in mind, thanks for the input!
Why wouldn't amd/valve to use lpddrx on same substrate to the main CPU like apple does on M series chip?
Cost.
Cost mostly, but the performance mat not be memory bandwidth limited. 8x rdna2 at relatively low clocks won't have huge bandwidth needs, and the needs of 4x Zen2 is minimal even with the cut-down L3$.
Someone needs to dump the Magic Leap 2's UEFI or chipset firmware to see how it's initializing those areas of the CPU...
Then IS possible to activate the IA on Steam deck LCD no !????
Wonderful video,
Probably this is the way how aliens decide we are still a primitive species of not.
All this miniaturization is impressive but at the same time the feeling that whe still use a 65 years old tech it's a bit depressing.
0:08 It's tiny! All that power from a pcb the size of an average phone.
Gaben *might* be some kind of wizard after all.
imagine if one day valve out of nowhere announced the steam decks can now be used for vr.
"Oh yeah that later version that is more expensive as well? Well you can't use that one, lol"
That would be dumb
DSP audio coprocessor?
Well, I forgot about magic leap entirely. I hope that was by their own choice.
TIL Zen 2 cores are made up of mostly branch prediction and cache and the actual "calculating" parts are tiny in area in comparison....
Lots of layers in that lithography. mb
Right DSP I lead on that release of this corporate said NPU it's a DSP I said a week ago, maybe back some time, but I am aware Tensilica, ARM, MIPS processors in FPGA fabrics with DSP for a very long time remember Brown Dwarf? mb
MIPS is better than ARM on DSP compliment in smart arial device. mb
there is a reorganized hand held market now that AMD has demonstrated a console SOC can make x2 cost = Price subject RA that is not a $22 a pop for 100 M units all up PS/5 or Xbox license payment the workstation data base is powered down sorry for the imprecision on the exact numbers. mb
Nice seeing you comment here
I wonder what else you could have put in that space for the visual processing and ML unit.
Maybe a Xilinx A.I engine or a Pensando DPU to handle networking and storage.
Yeah, there are other options too, I hope we will find for sure out at some point.