Road to Chiplets: Architecture - Dave Hiner: Chiplets: Building Blocks and Future Packaging Trends

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Chiplets: Building Blocks and Future Packaging Trends
Dave Hiner - Amkor Technology
Chiplets are the logical outcome of several factors affecting the IC industry’s drive towards higher and higher performance and to accomplish these requirements at a minimum total product cost. For this discussion, a chiplet is considered one of several functional blocks which normally resides inside a system-on-chip (SoC) design. Common chiplets are I/O die and CPU or compute chiplets.
Leading integrated circuit (IC) foundries are already shipping 7 nm and 5 nm process node wafers and will soon be shipping 3 nm. Wafer costs continue to soar as high transistor densities require more expensive processing for fabrication. Even with flat defect densities from node to node the cost per unit area of silicon is increasingly nonlinear. These base-level economics have caused a re-evaluation of the silicon chip design, fabrication and packaging technologies which serve current leading-edge and future high-performance products in the data center, personal computing and edge device segments.
Total product cost includes several important elements. Material costs including silicon and packaging are big drivers, with silicon costs usually dominating. Other important elements of total product cost include time-to-market (TTM) and design costs.
Chiplets allow functional blocks that require industry-leading transistor performance to be derived in the most current or suitable silicon node. A good example of these would be the CPU compute block. Other functional blocks, which do not need a leading-edge silicon node, could use N1 or N2 generation silicon. The results are physically smaller die or chiplets that can be combined and reused as needed to derive one or many different products. In this manner the design resource can design once and several functional blocks can conceptually use the same chiplet.
By using smaller chiplets (smaller than an SoC) wafer yields can be substantially increased and the cost per square millimeter of silicon for the total product can be reduced.
From an IC packaging standpoint, the broad approach of heterogeneous packaging has been the packaging industry’s contribution to this endeavor. The industry initiated this most recent effort for multi-die chiplet-based IC packaging with 2.5D Through Silicon Via (TSV) products. These allow very high-density DRAM (High Bandwidth Memory or HBM) to be implemented alongside the application-specific integrated circuit (ASIC) in the same IC package. In this instance, these dies were not chiplet based, at least initially, but the die-die interface density, very fine-pitch CuP bumping, and assembly methods were very similar to those needed by chiplet-based products.
To further refine our capabilities to address the chiplet-based heterogeneous package approach, Amkor has developed several key packaging technologies to permit several chiplets to be integrated into one product package.
Additionally, these chiplet blocks may also be integrated with dedicated ASICs and memory into one IC package. These end products include high-density multi-die offerings which use a conventional IC package substrate and Flip Chip BGA (FCBGAs) packages, as well as very fine-line constructions such as 2.5D TSV and High-Density Fan-Out (HDFO) offerings. New chiplet integrations using advanced HDFO (S-SWIFT™) are now being qualified to permit fine line routing down to 2 µm line and 2 µm space with 6-layer construction. This module fabrication technology has been developed over the last 3 years and upgraded to realistically permit the integration of chiplets and HBM designs.
The future of these packaging technologies is bright. New product designs in this packaging class have increased 4-fold over the previous year. The silicon architectural flexibility, IP reuse, time-to-market and lower overall cost continue to drive this innovation in the industry as Amkor delivers advances in heterogeneous IC packaging to meet the needs of a diverse set of chiplet-based designs.
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