#9 Behavioral modelling in verilog || Level of abstraction in logic design

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  • เผยแพร่เมื่อ 21 ธ.ค. 2024

ความคิดเห็น • 27

  • @mdarsad7694
    @mdarsad7694 3 ปีที่แล้ว +9

    You have explained very well
    Only you need to avoid your hesitation while making us understand

    • @ComponentByte
      @ComponentByte  3 ปีที่แล้ว +2

      I got it. I have tried to improve myself in the subsequent videos. Thanks.

  • @yatharthsaxena1926
    @yatharthsaxena1926 3 ปีที่แล้ว +2

    11:45 need not define sbar?

    • @ComponentByte
      @ComponentByte  3 ปีที่แล้ว +1

      Sorry, May be I missed because it's just an example.Thank you for the correction.

    • @hulkmania9487
      @hulkmania9487 2 ปีที่แล้ว

      @@ComponentByte it should be wire or reg ?

    • @ComponentByte
      @ComponentByte  2 ปีที่แล้ว

      You mean sbar? If so, then it's wire

  • @tshaw3782
    @tshaw3782 3 ปีที่แล้ว +4

    sir your videos are very helpful, kindly upload more videos of verilog

    • @ComponentByte
      @ComponentByte  3 ปีที่แล้ว +3

      Thank you very much.
      I have uploaded all most all the concepts of verilog. If you need something else related to verilog then you are most welcome to post here.

    • @tshaw3782
      @tshaw3782 3 ปีที่แล้ว +1

      @@ComponentByte thanks. But sir we need more videos of solving example in different types of module in verilog

  • @MuhammadShahzad-dx5je
    @MuhammadShahzad-dx5je 3 ปีที่แล้ว +2

    Hello sir? What exactly is RTL modeling? Is it the same as data flow ??

    • @ComponentByte
      @ComponentByte  3 ปีที่แล้ว +4

      No, it's not same as dataflow. RTL modeling gives information about how a code is implemented as real hardware and how data will be transferred between register and gates. So it's called register transfer level. This modeling defines digital ckt as combination of register and digital operation are performed between those register. This RTL code is input to synthesis tools. So any verilog code which is synthesized are called RTL code means the verilog code which has its corresponding optimized hardware or ckt is called RTL code. Visualise it once and you will get what I wrote. Thanks.

    • @MuhammadShahzad-dx5je
      @MuhammadShahzad-dx5je 3 ปีที่แล้ว +2

      @@ComponentByte Thank you so much sir 😊

  • @academicstuff548
    @academicstuff548 ปีที่แล้ว +1

    Great video sir.

  • @technicaldost9069
    @technicaldost9069 4 ปีที่แล้ว +1

    Informative..I also want to learn other concepts of verilog design.please make video

    • @ComponentByte
      @ComponentByte  4 ปีที่แล้ว +2

      Hey, I have not started the real verilog concepts so far..it's just a start. Next tutorial onwards you will learn all the Verilog concepts. Every details I will share in this channel. Thanks

  • @reshmas3714
    @reshmas3714 3 ปีที่แล้ว +1

    Thank you sir

  • @maxalex2055
    @maxalex2055 2 ปีที่แล้ว

    bro i am doing my major project on open source eda tool based on vlsi in which area,delay,power are main parameter to be consider my project name is Implementation and Physical Design of 8/4-Bit
    Signed Divider bro in this divider we are written module in behaviour model due to which we are getting problem in synthesis as i had seen in this video that behaviour modelling may be synthesis may not and does give information about the design connectivity in netlist and also this model is not considered as good for determine the parameter speed,delay bro pls guide me and tell me which model level will better for my major project and what modules are required in it designning

    • @ComponentByte
      @ComponentByte  2 ปีที่แล้ว

      While writing verilog code , it's always a benefit to follow RTL coding guidelines as the synthesis tool converts it into optimized hardware. It mostly depends on the logic design and then coding skill and synthesis tool we use. Different synthesis tools give different results and reports.
      So work on your logic because there should not be unnecessary lines in your code as it generates unwanted logic and hence consume power and silicon area and thus time.
      Some write code thinking in mind the real hardware.
      Some write code with the mindset to implement the logic only and thus end up writing C code .

    • @maxalex2055
      @maxalex2055 2 ปีที่แล้ว

      @@ComponentByte bro me and grp are using open source eda tool like iverilog and yosys and for backend we are using Ubuntu can you pls provide some kind of suggestions what to do and what not to do

    • @ComponentByte
      @ComponentByte  2 ปีที่แล้ว

      Your project seems to be very interesting but I have never worked on open source EDA and Ubuntu so I doubt , I can be service to you.

    • @maxalex2055
      @maxalex2055 2 ปีที่แล้ว

      @@ComponentByte thx you so much bro you said that you will support me that is big motivation for me and my team

  • @chintudewan1437
    @chintudewan1437 4 ปีที่แล้ว

    Got it.Thanx

  • @Manish_96_NITC
    @Manish_96_NITC 3 ปีที่แล้ว +1

    Bhai thoda short me batana next time

    • @ComponentByte
      @ComponentByte  3 ปีที่แล้ว +1

      I always try but it becomes long at the end and I also don't edit anything. So I will try next time.

    • @Manish_96_NITC
      @Manish_96_NITC 3 ปีที่แล้ว

      @@ComponentByte okay bhai