Thank you very much. I have uploaded all most all the concepts of verilog. If you need something else related to verilog then you are most welcome to post here.
No, it's not same as dataflow. RTL modeling gives information about how a code is implemented as real hardware and how data will be transferred between register and gates. So it's called register transfer level. This modeling defines digital ckt as combination of register and digital operation are performed between those register. This RTL code is input to synthesis tools. So any verilog code which is synthesized are called RTL code means the verilog code which has its corresponding optimized hardware or ckt is called RTL code. Visualise it once and you will get what I wrote. Thanks.
Hey, I have not started the real verilog concepts so far..it's just a start. Next tutorial onwards you will learn all the Verilog concepts. Every details I will share in this channel. Thanks
bro i am doing my major project on open source eda tool based on vlsi in which area,delay,power are main parameter to be consider my project name is Implementation and Physical Design of 8/4-Bit Signed Divider bro in this divider we are written module in behaviour model due to which we are getting problem in synthesis as i had seen in this video that behaviour modelling may be synthesis may not and does give information about the design connectivity in netlist and also this model is not considered as good for determine the parameter speed,delay bro pls guide me and tell me which model level will better for my major project and what modules are required in it designning
While writing verilog code , it's always a benefit to follow RTL coding guidelines as the synthesis tool converts it into optimized hardware. It mostly depends on the logic design and then coding skill and synthesis tool we use. Different synthesis tools give different results and reports. So work on your logic because there should not be unnecessary lines in your code as it generates unwanted logic and hence consume power and silicon area and thus time. Some write code thinking in mind the real hardware. Some write code with the mindset to implement the logic only and thus end up writing C code .
@@ComponentByte bro me and grp are using open source eda tool like iverilog and yosys and for backend we are using Ubuntu can you pls provide some kind of suggestions what to do and what not to do
You have explained very well
Only you need to avoid your hesitation while making us understand
I got it. I have tried to improve myself in the subsequent videos. Thanks.
11:45 need not define sbar?
Sorry, May be I missed because it's just an example.Thank you for the correction.
@@ComponentByte it should be wire or reg ?
You mean sbar? If so, then it's wire
sir your videos are very helpful, kindly upload more videos of verilog
Thank you very much.
I have uploaded all most all the concepts of verilog. If you need something else related to verilog then you are most welcome to post here.
@@ComponentByte thanks. But sir we need more videos of solving example in different types of module in verilog
Hello sir? What exactly is RTL modeling? Is it the same as data flow ??
No, it's not same as dataflow. RTL modeling gives information about how a code is implemented as real hardware and how data will be transferred between register and gates. So it's called register transfer level. This modeling defines digital ckt as combination of register and digital operation are performed between those register. This RTL code is input to synthesis tools. So any verilog code which is synthesized are called RTL code means the verilog code which has its corresponding optimized hardware or ckt is called RTL code. Visualise it once and you will get what I wrote. Thanks.
@@ComponentByte Thank you so much sir 😊
Great video sir.
Informative..I also want to learn other concepts of verilog design.please make video
Hey, I have not started the real verilog concepts so far..it's just a start. Next tutorial onwards you will learn all the Verilog concepts. Every details I will share in this channel. Thanks
Thank you sir
bro i am doing my major project on open source eda tool based on vlsi in which area,delay,power are main parameter to be consider my project name is Implementation and Physical Design of 8/4-Bit
Signed Divider bro in this divider we are written module in behaviour model due to which we are getting problem in synthesis as i had seen in this video that behaviour modelling may be synthesis may not and does give information about the design connectivity in netlist and also this model is not considered as good for determine the parameter speed,delay bro pls guide me and tell me which model level will better for my major project and what modules are required in it designning
While writing verilog code , it's always a benefit to follow RTL coding guidelines as the synthesis tool converts it into optimized hardware. It mostly depends on the logic design and then coding skill and synthesis tool we use. Different synthesis tools give different results and reports.
So work on your logic because there should not be unnecessary lines in your code as it generates unwanted logic and hence consume power and silicon area and thus time.
Some write code thinking in mind the real hardware.
Some write code with the mindset to implement the logic only and thus end up writing C code .
@@ComponentByte bro me and grp are using open source eda tool like iverilog and yosys and for backend we are using Ubuntu can you pls provide some kind of suggestions what to do and what not to do
Your project seems to be very interesting but I have never worked on open source EDA and Ubuntu so I doubt , I can be service to you.
@@ComponentByte thx you so much bro you said that you will support me that is big motivation for me and my team
Got it.Thanx
Bhai thoda short me batana next time
I always try but it becomes long at the end and I also don't edit anything. So I will try next time.
@@ComponentByte okay bhai