Blocking assignments can be used in both combinational and sequential circuits but nonblocking assignments can be used in sequential circuit only bcz of it's storage property. Blocking assignments blocks the execution of next statements until it is executed but In nonblocking multiple assignments happens at a same time.
4 initials blocks starts at time 0 and statements inside these are enclosed with begin- end and hence individual initial block's statements will be executed sequentially and therefore delays are accumulated inside those initial blocks. for example- inside 2nd initial block- ist statement ( a= 1'b1) will be executed at time 5 units and second statement (b= 1'b0) will be executed at [5 (delay because of ist statement)+ (delay assigned to 2nd statement=25) = 30 time units]
this is probably most important video so far
best playlist till now and will remain as best
Thank you mam
Your playlist is awesome
Thanks, Keep watching ✌✌
Thank you madam ❤❤
nice explanation....please make more such videos for verilog codes
Thanks Abhishek! Verilog coding videos will be uploaded soon. Stay connected ✌✌
@@vlsipoint Thank you
How to use blocking assignment with
continuous assignment ??
Mam in the last example of 4 bit counter why we take 4'd0 it should be 4'b0
It's in decimal
mam in 4x1 mux why you have declared OUTPUT as register ? Do we need to store the output ?
Yes mam , why we need to output as reg data type ???
@VLSI point
Great!!!!!!
Mam blocking assignment ka only combinationl circuit m hi q use hota h
Blocking assignments can be used in both combinational and sequential circuits but nonblocking assignments can be used in sequential circuit only bcz of it's storage property.
Blocking assignments blocks the execution of next statements until it is executed but In nonblocking multiple assignments happens at a same time.
very informative video !!
mam i want to ask doubts of verilog then can i ask you?
Maam I don’t understand about loop
Mem ek baar begin use karne par dobara kyon karte hain same code mein? Good playlist
Nice
Thanks Muskaan!
nice video
you haven't expalin what is %d,$monitor please do.
Here 3:27 statement result not understand
4 initials blocks starts at time 0 and statements inside these are enclosed with begin- end and hence individual initial block's statements will be executed sequentially and therefore delays are accumulated inside those initial blocks. for example- inside 2nd initial block- ist statement ( a= 1'b1) will be executed at time 5 units and second statement (b= 1'b0) will be executed at [5 (delay because of ist statement)+ (delay assigned to 2nd statement=25) = 30 time units]
Regular delay and Intra-assignment delay explanation looks same...
teaching so fast , as you think we know it already