Gate Level Modeling | #11 | Verilog in English | VLSI Point

[@kalyanidasari15]

Thank you so much for your lectures mam.. I feel confident as I complete your lectures.

[@sazzad96jewel]

Just awesome. Thank you mam for such videos..!💯

[@learning_page1234]

Your voice is too good, like you mam❤

[@theredtiger9239]

Thank you for the explanation maam. Only 1 thing, not gate and wire w1 are missing from the circuit at 11:10

[@mrtechindia]

Please tell any project related to verilog which is quite helpful to us to get job in VLSI

[@kolanaresh7077]

excellent mam.
mam please explain some mini projects also mam.

[@vlsipoint]

Okay Naresh, I'll try to give mini project.

[@aarafi493]

Thank you❤

[@YourRegularJon]

ma'am in the circuit example at 12 minutes, shouldn't xor x1 come after or o1 since w3 is an input in x1 but it isn't defined until o1 is called.

[@maruthikumar1759]

After 4 years I studied 3 hours continuously

[@renukahebballi9345]

ma'am i feel confident to work on program but can to explain the verilog program structure how to understand how to start

[@archanaarchana5315]

Awesome mam.! How long it will take to complete the course mam.?

[@vlsipoint]

Thanks Archana, probably by the next month course will be completed.

[@archanaarchana5315]

@@vlsipoint mam..one suggestion ...can you please explain through white board with your handwriting ...so it might be still more easy to understand and faster in concepts .Thankyou mam...!

[@jsttarun9754]

mam waiting for u...some more videos plsss

[@vlsipoint]

Sure Tarun, videos will be uploaded every week. Stay tuned✌

[@Amma4466]

Mam program starting loneg anni enduku rasaru

[@tejusvs4061]

mam can you provide notes/ppts of these lectures

[@thesailaja5941]

Even i stopped watching for 3 days and i started now , oh god what a coincidence😅😂😂😂

[@mrtechindia]

Can u provide notes of this lecture ma'am

[@vinivijay4811]

turn off delay 2nd point not clear mam